欢迎访问ic37.com |
会员登录 免费注册
发布采购

PIC18F24J10-I/SO 参数 Datasheet PDF下载

PIC18F24J10-I/SO图片预览
型号: PIC18F24J10-I/SO
PDF下载: 下载PDF文件 查看货源
内容描述: 28 /40/ 44引脚高性能, RISC微控制器 [28/40/44-Pin High-Performance, RISC Microcontrollers]
分类和应用: 微控制器
文件页数/大小: 368 页 / 5652 K
品牌: MICROCHIP [ MICROCHIP ]
 浏览型号PIC18F24J10-I/SO的Datasheet PDF文件第280页浏览型号PIC18F24J10-I/SO的Datasheet PDF文件第281页浏览型号PIC18F24J10-I/SO的Datasheet PDF文件第282页浏览型号PIC18F24J10-I/SO的Datasheet PDF文件第283页浏览型号PIC18F24J10-I/SO的Datasheet PDF文件第285页浏览型号PIC18F24J10-I/SO的Datasheet PDF文件第286页浏览型号PIC18F24J10-I/SO的Datasheet PDF文件第287页浏览型号PIC18F24J10-I/SO的Datasheet PDF文件第288页  
PIC18F45J10 FAMILY  
RLNCF  
Rotate Left f (No Carry)  
RRCF  
Rotate Right f through Carry  
Syntax:  
RLNCF f {,d {,a}}  
Syntax:  
RRCF f {,d {,a}}  
Operands:  
0 f 255  
d [0,1]  
a [0,1]  
Operands:  
0 f 255  
d [0,1]  
a [0,1]  
Operation:  
(f<n>) dest<n + 1>,  
(f<7>) dest<0>  
Operation:  
(f<n>) dest<n – 1>,  
(f<0>) C,  
(C) dest<7>  
Status Affected:  
Encoding:  
N, Z  
Status Affected:  
Encoding:  
C, N, Z  
0100  
01da  
ffff  
ffff  
0011  
00da  
ffff  
ffff  
Description:  
The contents of register ‘f’ are rotated  
one bit to the left. If ‘d’ is ‘0’, the result  
is placed in W. If ‘d’ is ‘1’, the result is  
stored back in register ‘f’ (default).  
If ‘a’ is ‘0’, the Access Bank is selected.  
If ‘a’ is ‘1’, the BSR is used to select the  
GPR bank (default).  
If ‘a’ is ‘0’ and the extended instruction  
set is enabled, this instruction operates  
in Indexed Literal Offset Addressing  
mode whenever f 95 (5Fh). See  
Section 22.2.3 “Byte-Oriented and  
Bit-Oriented Instructions in Indexed  
Literal Offset Mode” for details.  
Description:  
The contents of register ‘f’ are rotated  
one bit to the right through the Carry  
flag. If ‘d’ is ‘0’, the result is placed in W.  
If ‘d’ is ‘1’, the result is placed back in  
register ‘f’ (default).  
If ‘a’ is ‘0’, the Access Bank is selected.  
If ‘a’ is ‘1’, the BSR is used to select the  
GPR bank (default).  
If ‘a’ is ‘0’ and the extended instruction  
set is enabled, this instruction operates  
in Indexed Literal Offset Addressing  
mode whenever f 95 (5Fh). See  
Section 22.2.3 “Byte-Oriented and  
Bit-Oriented Instructions in Indexed  
Literal Offset Mode” for details.  
register f  
register f  
C
Words:  
Cycles:  
1
1
Words:  
Cycles:  
1
1
Q Cycle Activity:  
Q1  
Q2  
Q3  
Q4  
Q Cycle Activity:  
Q1  
Decode  
Read  
register ‘f’  
Process  
Data  
Write to  
destination  
Q2  
Q3  
Q4  
Decode  
Read  
register ‘f’  
Process  
Data  
Write to  
destination  
Example:  
RLNCF  
REG, 1, 0  
Before Instruction  
REG  
After Instruction  
Example:  
RRCF  
REG, 0, 0  
=
1010 1011  
0101 0111  
Before Instruction  
REG  
=
REG  
C
=
=
1110 0110  
0
After Instruction  
REG  
W
C
=
=
=
1110 0110  
0111 0011  
0
DS39682E-page 282  
© 2009 Microchip Technology Inc.  
 复制成功!