PIC18F45J10 FAMILY
TABLE 22-2: PIC18FXXXX INSTRUCTION SET
16-Bit Instruction Word
MSb LSb
Mnemonic,
Operands
Status
Affected
Description
Cycles
Notes
BYTE-ORIENTED OPERATIONS
ADDWF f, d, a Add WREG and f
ADDWFC f, d, a Add WREG and Carry bit to f
1
1
1
1
1
0010 01da
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff C, DC, Z, OV, N
ffff C, DC, Z, OV, N
ffff Z, N
1, 2
1, 2
1,2
2
1, 2
4
4
1, 2
1, 2, 3, 4
1, 2, 3, 4
1, 2
1, 2, 3, 4
4
1, 2
1, 2
1
0010 00da
0001 01da
0110 101a
0001 11da
ANDWF
CLRF
COMF
f, d, a AND WREG with f
f, a Clear f
f, d, a Complement f
ffff
Z
ffff Z, N
ffff None
ffff None
ffff None
ffff C, DC, Z, OV, N
ffff None
ffff None
ffff C, DC, Z, OV, N
ffff None
ffff None
ffff Z, N
ffff Z, N
ffff None
ffff
ffff None
ffff None
CPFSEQ
CPFSGT
CPFSLT
DECF
f, a
f, a
f, a
Compare f with WREG, Skip =
Compare f with WREG, Skip >
Compare f with WREG, Skip <
1 (2 or 3) 0110 001a
1 (2 or 3) 0110 010a
1 (2 or 3) 0110 000a
f, d, a Decrement f
1
0000 01da
DECFSZ
DCFSNZ
INCF
f, d, a Decrement f, Skip if 0
f, d, a Decrement f, Skip if Not 0
f, d, a Increment f
1 (2 or 3) 0010 11da
1 (2 or 3) 0100 11da
1
1 (2 or 3) 0011 11da
1 (2 or 3) 0100 10da
1
1
2
0010 10da
INCFSZ
INFSNZ
IORWF
MOVF
f, d, a Increment f, Skip if 0
f, d, a Increment f, Skip if Not 0
f, d, a Inclusive OR WREG with f
f, d, a Move f
0001 00da
0101 00da
1100 ffff
1111 ffff
0110 111a
0000 001a
0110 110a
0011 01da
0100 01da
0011 00da
0100 00da
0110 100a
0101 01da
MOVFF
f , f
Move f (source) to 1st Word
s
d
s
f (destination) 2nd Word
d
MOVWF
MULWF
NEGF
f, a
f, a
f, a
Move WREG to f
Multiply WREG with f
Negate f
1
1
1
1
1
1
1
1
1
1, 2
1, 2
ffff C, DC, Z, OV, N
ffff C, Z, N
ffff Z, N
ffff C, Z, N
ffff Z, N
RLCF
RLNCF
RRCF
RRNCF
SETF
f, d, a Rotate Left f through Carry
f, d, a Rotate Left f (No Carry)
f, d, a Rotate Right f through Carry
f, d, a Rotate Right f (No Carry)
f, a
Set f
ffff None
ffff C, DC, Z, OV, N
1, 2
1, 2
SUBFWB f, d, a Subtract f from WREG with
Borrow
SUBWF
f, d, a Subtract WREG from f
1
1
0101 11da
0101 10da
ffff
ffff
ffff C, DC, Z, OV, N
ffff C, DC, Z, OV, N
SUBWFB f, d, a Subtract WREG from f with
Borrow
SWAPF
TSTFSZ
XORWF
f, d, a Swap Nibbles in f
f, a Test f, Skip if 0
f, d, a Exclusive OR WREG with f
1
0011 10da
ffff
ffff
ffff
ffff None
ffff None
ffff Z, N
4
1, 2
1 (2 or 3) 0110 011a
0001 10da
1
Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value
present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an
external device, the data will be written back with a ‘0’.
2: If this instruction is executed on the TMR0 register (and where applicable, ‘d’ = 1), the prescaler will be cleared if
assigned.
3: If the Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second
cycle is executed as a NOP.
4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOPunless the
first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory
locations have a valid instruction.
DS39682E-page 252
© 2009 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
