PIC18F45J10 FAMILY
16.0 MASTER SYNCHRONOUS
SERIAL PORT (MSSP)
MODULE
Note:
In devices with more than one MSSP
module, it is very important to pay close
attention to SSPxCON register names.
SSP1CON1 and SSP1CON2 control
different operational aspects of the same
16.1 Master SSP (MSSP) Module
Overview
module,
while
SSP1CON1
and
SSP2CON1 control the same features for
two different modules.
The Master Synchronous Serial Port (MSSP) module is
a serial interface, useful for communicating with other
peripheral or microcontroller devices. These peripheral
devices may be serial EEPROMs, shift registers,
display drivers, A/D converters, etc. The MSSP module
can operate in one of two modes:
16.3 SPI Mode
The SPI mode allows 8 bits of data to be synchronously
transmitted and received simultaneously. All four
modes of SPI are supported. To accomplish
communication, typically three pins are used:
• Serial Peripheral Interface (SPI)
• Inter-Integrated Circuit (I2C™)
- Full Master mode
- Slave mode (with general address call)
The I2C interface supports the following modes in
hardware:
• Serial Data Out (SDOx) – RC5/SDO1 or
RD2/PSP2/SDO2
• Serial Data In (SDIx) – RC4/SDI1/SDA1 or
RD1/PSP1/SDI2/SDA2
• Serial Clock (SCKx) – RC3/SCK1/SCL1 or
RD0/PSP0/SCK2/SCL2
• Master mode
• Multi-Master mode
• Slave mode
Additionally, a fourth pin may be used when in a Slave
mode of operation:
PIC18F24J10/25J10 (28-pin) devices have one MSSP
module designated as MSSP1. PIC18F44J10/45J10
(40/44-pin) devices have two MSSP modules,
designated as MSSP1 and MSSP2. Each module
operates independently of the other.
• Slave Select (SSx) – RA5/AN4/SS1/C2OUT or
RD3/PSP3/SS2
Figure 16-1 shows the block diagram of the MSSP
module when operating in SPI mode.
Note:
Throughout this section, generic refer-
ences to an MSSP module in any of its
operating modes may be interpreted as
being equally applicable to MSSP1 or
MSSP2. Register names and module I/O
signals use the generic designator ‘x’ to
indicate the use of a numeral to distinguish
FIGURE 16-1:
MSSP BLOCK DIAGRAM
(SPI MODE)
Internal
Data Bus
Read
Write
SSPxBUF reg
a
particular module, when required.
Control bit names are not individuated.
SDIx
SSPxSR reg
Shift
16.2 Control Registers
SDOx
bit 0
Clock
Each MSSP module has three associated control
registers. These include a status register (SSPxSTAT)
and two control registers (SSPxCON1 and SSPxCON2).
The use of these registers and their individual configura-
tion bits differ significantly depending on whether the
MSSP module is operated in SPI or I2C mode.
SSx Control
Enable
SSx
Edge Select
Additional details are provided under the individual
sections.
2
Clock Select
Note:
Disabling the MSSP module by clearing
the SSPEN (SSPxCON1<5>) bit may not
reset the module. It is recommended to
clear the SSPxSTAT, SSPxCON1 and
SSPxCON2 registers and select the mode
prior to setting the SSPEN bit to enable
the MSSP module.
SSPM<3:0>
SMP:CKE
2
4
TMR2 Output
(
)
2
Edge
Select
TOSC
Prescaler
4, 16, 64
SCKx
Data to TX/RX in SSPxSR
TRIS bit
Note: Only port I/O names are used in this diagram for the sake
of brevity. Refer to the text for a full list of multiplexed
functions.
© 2009 Microchip Technology Inc.
DS39682E-page 149
MICROCHIP [ MICROCHIP ]
