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PIC18F2450-I/SO 参数 Datasheet PDF下载

PIC18F2450-I/SO图片预览
型号: PIC18F2450-I/SO
PDF下载: 下载PDF文件 查看货源
内容描述: 28 /40/ 44引脚,高性能, 12 MIPS ,增强型闪存, USB微控制器采用纳瓦技术 [28/40/44-Pin, High-Performance, 12 MIPS, Enhanced Flash, USB Microcontrollers with nanoWatt Technology]
分类和应用: 闪存微控制器和处理器外围集成电路光电二极管PC时钟
文件页数/大小: 320 页 / 5591 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC18F2450/4450  
CPFSGT  
Compare f with W, Skip if f > W  
CPFSLT  
Compare f with W, Skip if f < W  
Syntax:  
CPFSGT f {,a}  
Syntax:  
CPFSLT f {,a}  
Operands:  
0 f 255  
a [0,1]  
Operands:  
0 f 255  
a [0,1]  
Operation:  
(f) – (W),  
skip if (f) > (W)  
(unsigned comparison)  
Operation:  
(f) – (W),  
skip if (f) < (W)  
(unsigned comparison)  
Status Affected:  
Encoding:  
None  
Status Affected:  
Encoding:  
None  
0110  
0110  
010a  
ffff  
ffff  
000a  
ffff  
ffff  
Description:  
Compares the contents of data memory  
location ‘f’ to the contents of the W by  
performing an unsigned subtraction.  
If the contents of ‘f’ are greater than the  
contents of WREG, then the fetched  
instruction is discarded and a NOPis  
executed instead, making this a  
Description:  
Compares the contents of data memory  
location ‘f’ to the contents of W by  
performing an unsigned subtraction.  
If the contents of ‘f’ are less than the  
contents of W, then the fetched  
instruction is discarded and a NOPis  
executed instead, making this a  
two-cycle instruction.  
two-cycle instruction.  
If ‘a’ is ‘0’, the Access Bank is selected.  
If ‘a’ is ‘1’, the BSR is used to select the  
GPR bank (default).  
If ‘a’ is ‘0’ and the extended instruction  
set is enabled, this instruction operates  
in Indexed Literal Offset Addressing  
mode whenever f 95 (5Fh). See  
Section 19.2.3 “Byte-Oriented and  
Bit-Oriented Instructions in Indexed  
Literal Offset Mode” for details.  
If ‘a’ is ‘0’, the Access Bank is selected.  
If ‘a’ is ‘1’, the BSR is used to select the  
GPR bank (default).  
Words:  
Cycles:  
1
1(2)  
Note: 3 cycles if skip and followed  
by a 2-word instruction.  
Q Cycle Activity:  
Q1  
Q2  
Q3  
Q4  
Words:  
Cycles:  
1
Decode  
Read  
register ‘f’  
Process  
Data  
No  
operation  
1(2)  
Note: 3 cycles if skip and followed  
by a 2-word instruction.  
If skip:  
Q1  
Q2  
Q3  
Q4  
Q Cycle Activity:  
Q1  
No  
operation  
No  
operation  
No  
operation  
No  
operation  
Q2  
Read  
register ‘f’  
Q3  
Process  
Data  
Q4  
No  
operation  
Decode  
If skip and followed by 2-word instruction:  
If skip:  
Q1  
Q1  
Q2  
Q3  
Q4  
Q2  
No  
Q3  
No  
Q4  
No  
No  
operation  
No  
operation  
No  
operation  
No  
operation  
No  
operation  
operation  
operation  
operation  
No  
operation  
No  
operation  
No  
operation  
No  
operation  
If skip and followed by 2-word instruction:  
Q1  
No  
operation  
No  
Q2  
No  
operation  
No  
Q3  
No  
operation  
No  
Q4  
No  
operation  
No  
Example:  
HERE  
NLESS  
LESS  
CPFSLT REG, 1  
:
:
operation  
operation  
operation  
operation  
Before Instruction  
PC  
W
=
=
Address (HERE)  
Example:  
HERE  
NGREATER  
GREATER  
CPFSGT REG, 0  
:
:
?
After Instruction  
If REG  
PC  
If REG  
PC  
<
=
=
W;  
Before Instruction  
Address (LESS)  
W;  
PC  
W
=
=
Address (HERE)  
Address (NLESS)  
?
After Instruction  
If REG  
PC  
If REG  
PC  
>
=
=
W;  
Address (GREATER)  
W;  
Address (NGREATER)  
© 2006 Microchip Technology Inc.  
Advance Information  
DS39760A-page 229  
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