PIC18F2420/2520/4420/4520
Slave Select Synchronization............................................167
SLEEP...............................................................................302
Sleep
OSC1 and OSC2 Pin States.......................................31
Software Simulator (MPLAB SIM).....................................318
Special Event Trigger. See Compare (ECCP Mode).
Special Event Trigger. See Compare (ECCP Module).
Special Features of the CPU.............................................249
Special Function Registers
Timer1............................................................................... 127
16-Bit Read/Write Mode ........................................... 129
Associated Registers................................................ 132
Considerations in Asynchronous
Counter Mode................................................... 131
Interrupt .................................................................... 130
Operation.................................................................. 128
Oscillator........................................................... 127, 129
Oscillator Layout Considerations.............................. 130
Overflow Interrupt ..................................................... 127
Resetting, Using the CCP Special
Map.............................................................................63
SPI Mode (MSSP)
Associated Registers ................................................169
Bus Mode Compatibility ............................................169
Effects of a Reset......................................................169
Enabling SPI I/O .......................................................165
Master Mode.............................................................166
Master/Slave Connection..........................................165
Operation ..................................................................164
Operation in Power-Managed Modes .......................169
Serial Clock...............................................................161
Serial Data In ............................................................161
Serial Data Out .........................................................161
Slave Mode...............................................................167
Slave Select..............................................................161
Slave Select Synchronization ...................................167
SPI Clock ..................................................................166
Typical Connection ...................................................165
SS .....................................................................................161
SSPOV..............................................................................191
SSPOV Status Flag...........................................................191
SSPSTAT Register
R/W Bit..............................................................174, 175
Stack Full/Underflow Resets...............................................56
STATUS Register................................................................67
SUBFSR............................................................................313
SUBFWB...........................................................................302
SUBLW .............................................................................303
SUBULNK .........................................................................313
SUBWF .............................................................................303
SUBWFB...........................................................................304
SWAPF .............................................................................304
Event Trigger.................................................... 130
Special Event Trigger (ECCP).................................. 148
TMR1H Register....................................................... 127
TMR1L Register........................................................ 127
Use as a Real-Time Clock........................................ 130
Timer2............................................................................... 133
Associated Registers................................................ 134
Interrupt .................................................................... 134
Operation.................................................................. 133
Output....................................................................... 134
PR2 Register .................................................... 144, 149
TMR2 to PR2 Match Interrupt........................... 144, 149
Timer3............................................................................... 135
16-Bit Read/Write Mode ........................................... 137
Associated Registers................................................ 137
Operation.................................................................. 136
Oscillator........................................................... 135, 137
Overflow Interrupt ............................................. 135, 137
Special Event Trigger (CCP) .................................... 137
TMR3H Register....................................................... 135
TMR3L Register........................................................ 135
Timing Diagrams
A/D Conversion......................................................... 360
Acknowledge Sequence........................................... 194
Asynchronous Reception.......................................... 214
Asynchronous Transmission..................................... 212
Asynchronous Transmission (Back to Back) ............ 212
Automatic Baud Rate Calculation............................. 210
Auto-Wake-up Bit (WUE) During
Normal Operation ............................................. 215
Auto-Wake-up Bit (WUE) During Sleep.................... 215
Baud Rate Generator with Clock Arbitration............. 188
BRG Overflow Sequence.......................................... 210
BRG Reset Due to SDA Arbitration
During Start Condition ...................................... 197
Brown-out Reset (BOR)............................................ 345
Bus Collision During a Repeated
Start Condition (Case 1)................................... 198
Bus Collision During a Repeated
Start Condition (Case 2)................................... 198
Bus Collision During a Start
Condition (SCL = 0).......................................... 197
Bus Collision During a Stop
Condition (Case 1)............................................ 199
Bus Collision During a Stop
Condition (Case 2)............................................ 199
Bus Collision During Start
T
Table Pointer Operations with
TBLRD and TBLWT ....................................................76
Table Reads/Table Writes...................................................56
TBLRD ..............................................................................305
TBLWT..............................................................................306
Time-out in Various Situations (table).................................45
Timer0...............................................................................123
Associated Registers ................................................125
Operation ..................................................................124
Overflow Interrupt .....................................................125
Prescaler...................................................................125
Prescaler Assignment (PSA Bit) ...............................125
Prescaler Select (T0PS2:T0PS0 Bits) ......................125
Prescaler. See Prescaler, Timer0.
Reads and Writes in 16-Bit Mode .............................124
Source Edge Select (T0SE Bit).................................124
Source Select (T0CS Bit)..........................................124
Switching Prescaler Assignment...............................125
Condition (SDA only)........................................ 196
Bus Collision for Transmit and Acknowledge ........... 195
Capture/Compare/PWM (All CCP Modules)............. 347
DS39631E-page 404
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