PIC18F2420/2520/4420/4520
The analog reference voltage is software selectable to
either the device’s positive and negative supply voltage
(VDD and VSS), or the voltage level on the RA3/AN3/
VREF+ and RA2/AN2/VREF-/CVREF pins.
A device Reset forces all registers to their Reset state.
This forces the A/D module to be turned off and any
conversion in progress is aborted.
Each port pin associated with the A/D Converter can be
configured as an analog input, or as a digital I/O. The
ADRESH and ADRESL registers contain the result of the
A/D conversion. When the A/D conversion is complete,
the result is loaded into the ADRESH:ADRESL register
pair, the GO/DONE bit (ADCON0 register) is cleared and
the A/D Interrupt Flag bit, ADIF, is set. The block diagram
of the A/D module is shown in Figure 19-1.
The A/D Converter has a unique feature of being able
to operate while the device is in Sleep mode. To oper-
ate in Sleep, the A/D conversion clock must be derived
from the A/D’s internal RC oscillator.
The output of the sample and hold is the input into the
converter, which generates the result via successive
approximation.
FIGURE 19-1:
A/D BLOCK DIAGRAM
CHS<3:0>
1100
AN12
1011
AN11
1010
AN10
1001
AN9
1000
AN8
0111
AN7(1)
0110
AN6(1)
0101
AN5(1)
0100
AN4
VAIN
0011
(Input Voltage)
10-Bit
A/D
Converter
AN3
0010
AN2
0001
VCFG<1:0>
AN1
(2)
0000
VDD
X0
AN0
VREF+
VREF-
X1
1X
Reference
Voltage
0X
(2)
VSS
Note 1: Channels, AN5 through AN7, are not available on 28-pin devices.
2: I/O pins have diode protection to VDD and VSS.
DS39631E-page 226
© 2008 Microchip Technology Inc.
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