PIC18F2420/2520/4420/4520
FIGURE 1-2:
Table Pointer<21>
inc/dec logic
21
20
8
PCLATU PCLATH
PIC18F4420/4520 (40/44-PIN) BLOCK DIAGRAM
Data Bus<8>
Data Latch
Data Memory
( 3.9 Kbytes )
Address Latch
12
Data Address<12>
4
BSR
12
FSR0
FSR1
FSR2
inc/dec
logic
4
Access
Bank
12
PORTA
RA0/AN0
RA1/AN1
RA2/AN2/V
REF
-/CV
REF
RA3/AN3/V
REF
+
RA4/T0CKI/C1OUT
RA5/AN4/SS/HLVDIN/C2OUT
OSC2/CLKO
(3)
/RA6
OSC1/CLKI
(3)
/RA7
PORTB
RB0/INT0/FLT0/AN12
RB1/INT1/AN10
RB2/INT2/AN8
RB3/AN9/CCP2
(1)
RB4/KBI0/AN11
RB5/KBI1/PGM
RB6/KBI2/PGC
RB7/KBI3/PGD
8
PCU PCH PCL
Program Counter
31-Level Stack
Address Latch
Program Memory
(16/32 Kbytes)
Data Latch
8
STKPTR
Table Latch
ROM Latch
Instruction Bus <16>
IR
Address
Decode
PORTC
RC0/T1OSO/T13CKI
RC1/T1OSI/CCP2
(1)
RC2/CCP1/P1A
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK
RC7/RX/DT
Instruction
Decode and
Control
State Machine
Control Signals
8
PRODH PRODL
3
BITOP
8
8 x 8 Multiply
8
W
8
8
ALU<8>
8
PORTE
Precision
Band Gap
Reference
8
8
PORTD
RD0/PSP0 :RD4/PSP4
RD5/PSP5/P1B
RD6/PSP6/P1C
RD7/PSP7/P1D
OSC1
(3)
OSC2
(3)
T1OSI
T1OSO
MCLR
(2)
V
DD
, V
SS
Internal
Oscillator
Block
INTRC
Oscillator
8 MHz
Oscillator
Single-Supply
Programming
In-Circuit
Debugger
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Brown-out
Reset
Fail-Safe
Clock Monitor
RE0/RD/AN5
RE1/WR/AN6
RE2/CS/AN7
MCLR/V
PP
/RE3
(2)
BOR
HLVD
Data
EEPROM
Timer0
Timer1
Timer2
Timer3
Comparator
ECCP1
CCP2
MSSP
EUSART
ADC
10-Bit
Note
1:
2:
3:
CCP2 is multiplexed with RC1 when Configuration bit, CCP2MX, is set, or RB3 when CCP2MX is not set.
RE3 is only available when MCLR functionality is disabled.
OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O.
Refer to
for additional information.
©
2008 Microchip Technology Inc.
DS39631E-page 11
MICROCHIP [ MICROCHIP TECHNOLOGY ]
