PIC18F45J10 FAMILY
FIGURE 9-1:
PIC18F24J10/25J10/44J10/45J10 INTERRUPT LOGIC
Wake-up if in
Idle or Sleep modes
TMR0IF
TMR0IE
TMR0IP
RBIF
RBIE
RBIP
INT0IF
INT0IE
INT1IF
INT1IE
INT1IP
INT2IF
INT2IE
INT2IP
Interrupt to CPU
Vector to Location
0008h
PIR1<7:0>
PIE1<7:0>
IPR1<7:0>
GIE/GIEH
PIR2<7:6, 3, 0>
PIE2<7:6, 3, 0>
IPR2<7:6, 3, 0>
IPEN
PIR3<7:6>
PIE3<7:6>
IPR3<7:6>
IPEN
PEIE/GIEL
IPEN
High-Priority Interrupt Generation
Low-Priority Interrupt Generation
PIR1<7:0>
PIE1<7:0>
IPR1<7:0>
PIR2<7:6, 3, 0>
PIE2<7:6, 3, 0>
IPR2<7:6, 3, 0>
Interrupt to CPU
Vector to Location
0018h
TMR0IF
TMR0IE
TMR0IP
IPEN
PIR3<7:6>
PIE3<7:6>
IPR3<7:6>
RBIF
RBIE
RBIP
GIE/GIEH
PEIE/GIEL
INT1IF
INT1IE
INT1IP
INT2IF
INT2IE
INT2IP
DS39682E-page 84
© 2009 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
