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PIC18F25J10-I/SS 参数 Datasheet PDF下载

PIC18F25J10-I/SS图片预览
型号: PIC18F25J10-I/SS
PDF下载: 下载PDF文件 查看货源
内容描述: 28 /40/ 44引脚高性能, RISC微控制器 [28/40/44-Pin High-Performance, RISC Microcontrollers]
分类和应用: 微控制器和处理器外围集成电路光电二极管PC时钟
文件页数/大小: 368 页 / 5652 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC18F45J10 FAMILY  
6.2.2  
INSTRUCTION FLOW/PIPELINING  
6.2  
PIC18 Instruction Cycle  
An “Instruction Cycle” consists of four Q cycles: Q1  
through Q4. The instruction fetch and execute are  
pipelined in such a manner that a fetch takes one  
instruction cycle, while the decode and execute take  
another instruction cycle. However, due to the pipe-  
lining, each instruction effectively executes in one  
cycle. If an instruction causes the program counter to  
change (e.g., GOTO), then two cycles are required to  
complete the instruction (Example 6-3).  
6.2.1  
CLOCKING SCHEME  
The microcontroller clock input, whether from an  
internal or external source, is internally divided by four  
to generate four non-overlapping quadrature clocks  
(Q1, Q2, Q3 and Q4). Internally, the program counter is  
incremented on every Q1; the instruction is fetched  
from the program memory and latched into the instruc-  
tion register during Q4. The instruction is decoded and  
executed during the following Q1 through Q4. The  
clocks and instruction execution flow are shown in  
Figure 6-4.  
A fetch cycle begins with the Program Counter (PC)  
incrementing in Q1.  
In the execution cycle, the fetched instruction is latched  
into the Instruction Register (IR) in cycle Q1. This  
instruction is then decoded and executed during the  
Q2, Q3 and Q4 cycles. Data memory is read during Q2  
(operand read) and written during Q4 (destination  
write).  
FIGURE 6-4:  
CLOCK/INSTRUCTION CYCLE  
Q2  
Q3  
Q4  
Q2  
Q3  
Q4  
Q2  
Q3  
Q4  
Q1  
Q1  
Q1  
OSC1  
Q1  
Q2  
Q3  
Q4  
Internal  
Phase  
Clock  
PC  
PC  
PC + 2  
PC + 4  
OSC2/CLKO  
(RC mode)  
Execute INST (PC – 2)  
Fetch INST (PC)  
Execute INST (PC)  
Fetch INST (PC + 2)  
Execute INST (PC + 2)  
Fetch INST (PC + 4)  
EXAMPLE 6-3:  
INSTRUCTION PIPELINE FLOW  
TCY0  
TCY1  
TCY2  
TCY3  
TCY4  
TCY5  
1. MOVLW 55h  
2. MOVWF PORTB  
3. BRA SUB_1  
Fetch 1  
Execute 1  
Fetch 2  
Execute 2  
Fetch 3  
Execute 3  
Fetch 4  
4. BSF  
PORTA, BIT3 (Forced NOP)  
Flush (NOP)  
5. Instruction @ address SUB_1  
Fetch SUB_1 Execute SUB_1  
All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction  
is “flushed” from the pipeline while the new instruction is being fetched and then executed.  
DS39682E-page 56  
© 2009 Microchip Technology Inc.  
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