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PIC18F25J10-I/SS 参数 Datasheet PDF下载

PIC18F25J10-I/SS图片预览
型号: PIC18F25J10-I/SS
PDF下载: 下载PDF文件 查看货源
内容描述: 28 /40/ 44引脚高性能, RISC微控制器 [28/40/44-Pin High-Performance, RISC Microcontrollers]
分类和应用: 微控制器和处理器外围集成电路光电二极管PC时钟
文件页数/大小: 368 页 / 5652 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC18F45J10 FAMILY  
6.1.4.4  
Stack Full and Underflow Resets  
6.1.6  
LOOK-UP TABLES IN PROGRAM  
MEMORY  
Device Resets on stack overflow and stack underflow  
conditions are enabled by setting the STVREN bit in  
Configuration Register 4L. When STVREN is set, a full  
or underflow will set the appropriate STKFUL or  
STKUNF bit and then cause a device Reset. When  
STVREN is cleared, a full or underflow condition will set  
the appropriate STKFUL or STKUNF bit but not cause  
a device Reset. The STKFUL or STKUNF bits are  
cleared by the user software or a Power-on Reset.  
There may be programming situations that require the  
creation of data structures, or look-up tables, in  
program memory. For PIC18 devices, look-up tables  
can be implemented in two ways:  
• Computed GOTO  
Table Reads  
6.1.6.1  
Computed GOTO  
6.1.5  
FAST REGISTER STACK  
A computed GOTOis accomplished by adding an offset  
to the program counter. An example is shown in  
Example 6-2.  
A Fast Register Stack is provided for the STATUS,  
WREG and BSR registers, to provide a “fast return”  
option for interrupts. The stack for each register is only  
one level deep and is neither readable nor writable. It is  
loaded with the current value of the corresponding  
register when the processor vectors for an interrupt. All  
interrupt sources will push values into the stack regis-  
ters. The values in the registers are then loaded back  
into their associated registers if the RETFIE, FAST  
instruction is used to return from the interrupt.  
A look-up table can be formed with an ADDWF PCL  
instruction and a group of RETLW nninstructions. The  
W register is loaded with an offset into the table before  
executing a call to that table. The first instruction of the  
called routine is the ADDWF PCLinstruction. The next  
instruction executed will be one of the RETLW nn  
instructions that returns the value ‘nn’ to the calling  
function.  
If both low and high-priority interrupts are enabled, the  
stack registers cannot be used reliably to return from  
low-priority interrupts. If a high-priority interrupt occurs  
while servicing a low-priority interrupt, the stack regis-  
ter values stored by the low-priority interrupt will be  
overwritten. In these cases, users must save the key  
registers in software during a low-priority interrupt.  
The offset value (in WREG) specifies the number of  
bytes that the program counter should advance and  
should be multiples of 2 (LSb = 0).  
In this method, only one data byte may be stored in  
each instruction location and room on the return  
address stack is required.  
If interrupt priority is not used, all interrupts may use the  
Fast Register Stack for returns from interrupt. If no  
interrupts are used, the Fast Register Stack can be  
used to restore the STATUS, WREG and BSR registers  
at the end of a subroutine call. To use the Fast Register  
Stack for a subroutine call, a CALL label, FAST  
instruction must be executed to save the STATUS,  
WREG and BSR registers to the Fast Register Stack. A  
RETURN, FASTinstruction is then executed to restore  
these registers from the Fast Register Stack.  
EXAMPLE 6-2:  
COMPUTED GOTO USING  
AN OFFSET VALUE  
OFFSET, W  
TABLE  
MOVF  
CALL  
ORG  
TABLE  
nn00h  
ADDWF  
RETLW  
RETLW  
RETLW  
.
PCL  
nnh  
nnh  
nnh  
.
.
Example 6-1 shows a source code example that uses  
the Fast Register Stack during a subroutine call and  
return.  
6.1.6.2  
Table Reads and Table Writes  
A better method of storing data in program memory  
allows two bytes of data to be stored in each instruction  
location.  
EXAMPLE 6-1:  
FAST REGISTER STACK  
CODE EXAMPLE  
CALL SUB1, FAST  
;STATUS, WREG, BSR  
;SAVED IN FAST REGISTER  
;STACK  
Look-up table data may be stored two bytes per pro-  
gram word by using table reads and writes. The Table  
Pointer (TBLPTR) register specifies the byte address  
and the Table Latch (TABLAT) register contains the  
data that is read from or written to program memory.  
Data is transferred to or from program memory one  
byte at a time.  
SUB1  
RETURN, FAST  
;RESTORE VALUES SAVED  
;IN FAST REGISTER STACK  
Table read and table write operations are discussed  
further in Section 7.1 “Table Reads and Table  
Writes”.  
© 2009 Microchip Technology Inc.  
DS39682E-page 55  
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