PIC18F45J10 FAMILY
Pin Diagrams (Continued)
40-Pin PDIP (600 MIL)
= Pins are up to 5.5V tolerant
MCLR
RA0/AN0
1
2
3
4
5
6
7
8
RB7/KBI3/PGD
RB6/KBI2/PGC
RB5/KBI1/T0CKI/C1OUT
RB4/KBI0/AN11
RB3/AN9/CCP2*
RB2/INT2/AN8
40
39
RA1/AN1
RA2/AN2/VREF-/CVREF
38
37
RA3/AN3/VREF+
VDDCORE/VCAP
36
35
RA5/AN4/SS1/C2OUT
RE0/RD/AN5
RE1/WR/AN6
RE2/CS/AN7
VDD
VSS
OSC1/CLKI
OSC2/CLKO
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2*
RC2/CCP1/P1A
RB1/INT1/AN10
RB0/INT0/FLT0/AN12
VDD
32
VSS
31
34
33
9
10
11
12
13
14
15
16
17
18
RD7/PSP7/P1D
RD6/PSP6/P1C
RD5/PSP5/P1B
RD4/PSP4
RC7/RX/DT
RC6/TX/CK
RC5/SDO1
30
29
28
27
26
25
24
RC3/SCK1/SCL1
RC4/SDI1/SDA1
23
RD0/PSP0/SCK2/SCL2
RD3/PSP3/SS2
19
20
22
RD1/PSP1/SDI2/SDA2
RD2/PSP2/SDO2
21
* Pin feature is dependent on device configuration.
.
44-Pin QFN(1)
= Pins are up to 5.5V tolerant
OSC2/CLKO
OSC1/CLKI
VSS
VSS
VDD
RC7/RX/DT
RD4/PSP4
RD5/PSP5/P1B
RD6/PSP6/P1C
1
33
32
31
30
29
28
27
26
25
24
23
2
3
4
5
6
7
8
9
10
11
RD7/PSP7/P1D
PIC18F44J10
PIC18F45J10
VDD
VSS
VDD
VDD
RE2/CS/AN7
RE1/WR/AN6
RE0/RD/AN5
RA5/AN4/SS1/C2OUT
VDDCORE/VCAP
RB0/INT0/FLT0/AN12
RB1/INT1/AN10
RB2/INT2/AN8
* Pin feature is dependent on device configuration.
Note 1: For the QFN package, it is recommended that the bottom pad be connected to VSS.
© 2009 Microchip Technology Inc.
DS39682E-page 3
MICROCHIP [ MICROCHIP ]
