PIC18F45J10 FAMILY
CMCON (Comparator Control) ................................ 225
CONFIG1H (Configuration 1 High) .......................... 237
CONFIG1L (Configuration 1 Low) ............................ 237
CONFIG2H (Configuration 2 High) .......................... 239
CONFIG2L (Configuration 2 Low) ............................ 238
CONFIG3H (Configuration 3 High) .......................... 240
CONFIG3L (Configuration 3 Low) ............................ 240
CVRCON (Comparator Voltage
Return Stack Pointer (STKPTR) ........................................ 54
Revision History ............................................................... 349
RLCF ............................................................................... 281
RLNCF ............................................................................. 282
RRCF ............................................................................... 282
RRNCF ............................................................................ 283
S
SCKx ............................................................................... 149
SDIx ................................................................................. 149
SDOx ............................................................................... 149
SEC_IDLE Mode ............................................................... 39
SEC_RUN Mode ................................................................ 36
Serial Clock, SCKx .......................................................... 149
Serial Data In (SDIx) ........................................................ 149
Serial Data Out (SDOx) ................................................... 149
Serial Peripheral Interface. See SPI Mode.
SETF ............................................................................... 283
Slave Select (SSx) ........................................................... 149
SLEEP ............................................................................. 284
Sleep
OSC1 and OSC2 Pin States ...................................... 33
Software Simulator (MPLAB SIM) ................................... 300
Special Event Trigger. See Compare (ECCP Module).
Special Event Trigger. See Compare (ECCP/CCP Modules).
Special Features of the CPU ........................................... 235
Special Function Registers ................................................ 61
Map ............................................................................ 61
SPI Mode (MSSP)
Reference Control) .......................................... 231
DEVID1 (Device ID Register 1) ................................ 241
DEVID2 (Device ID Register 2) ................................ 241
ECCP1DEL (PWM Dead-Band Delay) .................... 144
EECON1 (EEPROM Control 1) .................................. 73
EUSART Receive Status and Control ...................... 195
INTCON (Interrupt Control) ........................................ 85
INTCON2 (Interrupt Control 2) ................................... 86
INTCON3 (Interrupt Control 3) ................................... 87
IPR1 (Peripheral Interrupt Priority 1) .......................... 92
IPR2 (Peripheral Interrupt Priority 2) .......................... 93
IPR3 (Peripheral Interrupt Priority 3) .......................... 93
OSCCON (Oscillator Control) .................................... 32
OSCTUNE (PLL Control) ........................................... 29
PIE1 (Peripheral Interrupt Enable 1) .......................... 90
PIE2 (Peripheral Interrupt Enable 2) .......................... 91
PIE3 (Peripheral Interrupt Enable 3) .......................... 91
PIR1 (Peripheral Interrupt Request (Flag) 1) ............. 88
PIR2 (Peripheral Interrupt Request (Flag) 2) ............. 89
PIR3 (Peripheral Interrupt Request (Flag) 3) ............. 89
RCON (Reset Control) ......................................... 42, 94
2
Associated Registers ............................................... 158
Bus Mode Compatibility ........................................... 157
Clock Speed and Module Interactions ..................... 157
Effects of a Reset .................................................... 157
Enabling SPI I/O ...................................................... 153
Master Mode ............................................................ 154
Master/Slave Connection ........................................ 153
Operation ................................................................. 152
Operation in Power-Managed Modes ...................... 157
Serial Clock ............................................................. 149
Serial Data In ........................................................... 149
Serial Data Out ........................................................ 149
Slave Mode .............................................................. 155
Slave Select ............................................................. 149
Slave Select Synchronization .................................. 155
SPI Clock ................................................................. 154
Typical Connection .................................................. 153
SSPOV ............................................................................ 182
SSPOV Status Flag ......................................................... 182
SSPxSTAT Register
R/W Bit ............................................................ 164, 166
SSx .................................................................................. 149
Stack Full/Underflow Resets .............................................. 55
STATUS Register .............................................................. 65
SUBFSR .......................................................................... 295
SUBFWB ......................................................................... 284
SUBLW ............................................................................ 285
SUBULNK ........................................................................ 295
SUBWF ............................................................................ 285
SUBWFB ......................................................................... 286
SWAPF ............................................................................ 286
SSPxCON1 (MSSPx Control 1, I C Mode) .............. 161
SSPxCON1 (MSSPx Control 1, SPI Mode) ............. 151
SSPxCON2 (MSSPx Control 2,
2
I C Master Mode) ............................................ 162
SSPxCON2 (MSSPx Control 2,
2
I C Slave Mode) .............................................. 163
2
SSPxSTAT (MSSPx Status, I C Mode) ................... 160
SSPxSTAT (MSSPx Status, SPI Mode) .................. 150
STATUS ..................................................................... 65
STKPTR (Stack Pointer) ............................................ 54
T0CON (Timer0 Control) .......................................... 115
T1CON (Timer1 Control) .......................................... 119
T2CON (Timer2 Control) .......................................... 125
TRISE (PORTE/PSP Control) .................................. 111
TXSTA (EUSART Transmit Status
and Control) ..................................................... 194
WDTCON (Watchdog Timer Control) ...................... 242
RESET ............................................................................. 279
Reset
Brown-out Reset (BOR) ............................................. 41
Configuration Mismatch (CM) .................................... 41
MCLR Reset, During Power-Managed Modes ........... 41
MCLR Reset, Normal Operation ................................ 41
Power-on Reset (POR) .............................................. 41
RESET Instruction ..................................................... 41
Stack Full Reset ......................................................... 41
Stack Underflow Reset .............................................. 41
Watchdog Timer (WDT) Reset ................................... 41
Resets .............................................................................. 235
Brown-out Reset (BOR) ........................................... 235
Oscillator Start-up Timer (OST) ............................... 235
Power-on Reset (POR) ............................................ 235
Power-up Timer (PWRT) ......................................... 235
RETFIE ............................................................................ 280
RETLW ............................................................................ 280
RETURN .......................................................................... 281
Return Address Stack ........................................................ 53
T
Table Pointer Operations (table) ........................................ 74
Table Reads/Table Writes ................................................. 55
TBLRD ............................................................................. 287
TBLWT ............................................................................ 288
© 2009 Microchip Technology Inc.
DS39682E-page 359
MICROCHIP [ MICROCHIP ]
