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PIC18F25J10-I/SS 参数 Datasheet PDF下载

PIC18F25J10-I/SS图片预览
型号: PIC18F25J10-I/SS
PDF下载: 下载PDF文件 查看货源
内容描述: 28 /40/ 44引脚高性能, RISC微控制器 [28/40/44-Pin High-Performance, RISC Microcontrollers]
分类和应用: 微控制器和处理器外围集成电路光电二极管PC时钟
文件页数/大小: 368 页 / 5652 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC18F45J10 FAMILY  
FIGURE 19-3:  
COMPARATOR OUTPUT BLOCK DIAGRAM  
Port Pins  
To RB5 or  
RA5 pin  
D
Q
Bus  
Data  
CxINV  
EN  
Read CMCON  
D
Q
Set  
CMIF  
bit  
EN  
CL  
From  
Other  
Comparator  
Reset  
19.6 Comparator Interrupts  
19.7 Comparator Operation  
During Sleep  
The comparator interrupt flag is set whenever there is  
a change in the output value of either comparator.  
Software will need to maintain information about the  
status of the output bits, as read from CMCON<7:6>, to  
determine the actual change that occurred. The CMIF  
bit (PIR2<6>) is the Comparator Interrupt Flag. The  
CMIF bit must be reset by clearing it. Since it is also  
possible to write a ‘1’ to this register, a simulated  
interrupt may be initiated.  
When a comparator is active and the device is placed  
in Sleep mode, the comparator remains active and the  
interrupt is functional, if enabled. This interrupt will  
wake-up the device from Sleep mode, when enabled.  
Each operational comparator will consume additional  
current, as shown in the comparator specifications. To  
minimize power consumption while in Sleep mode, turn  
off the comparators (CM<2:0> = 111) before entering  
Sleep. If the device wakes up from Sleep, the contents  
of the CMCON register are not affected.  
Both the CMIE bit (PIE2<6>) and the PEIE bit  
(INTCON<6>) must be set to enable the interrupt. In  
addition, the GIE bit (INTCON<7>) must also be set. If  
any of these bits are clear, the interrupt is not enabled,  
though the CMIF bit will still be set if an interrupt  
condition occurs.  
19.8 Effects of a Reset  
A device Reset forces the CMCON register to its Reset  
state, causing the comparator modules to be turned off  
(CM<2:0> = 111). However, the input pins (RA0  
through RA3) are configured as analog inputs by  
default on device Reset. The I/O configuration for these  
pins is determined by the setting of the PCFG<3:0> bits  
(ADCON1<3:0>). Therefore, device current is  
minimized when analog inputs are present at Reset  
time.  
Note:  
If a change in the CMCON register  
(C1OUT or C2OUT) should occur when a  
read operation is being executed (start of  
the Q2 cycle), then the CMIF (PIR2  
register) interrupt flag may not get set.  
The user, in the Interrupt Service Routine, can clear the  
interrupt in the following manner:  
a) Any read or write of CMCON will end the  
mismatch condition.  
b) Clear flag bit CMIF.  
A mismatch condition will continue to set flag bit, CMIF.  
Reading CMCON will end the mismatch condition and  
allow flag bit, CMIF, to be cleared.  
DS39682E-page 228  
© 2009 Microchip Technology Inc.