PIC18F45J10 FAMILY
TABLE 16-4: REGISTERS ASSOCIATED WITH I2C™ OPERATION
Reset
Values
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
PIR1
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TXIF
TXIE
TXIP
—
RBIE
SSP1IF
SSP1IE
SSP1IP
BCL1IF
BCL1IE
BCL1IP
—
TMR0IF
CCP1IF
CCP1IE
CCP1IP
—
INT0IF
RBIF
47
49
49
49
49
49
49
49
49
49
50
50
48
48
PSPIF(1)
PSPIE(1)
PSPIP(1)
OSCFIF
OSCFIE
OSCFIP
SSP2IF
SSP2IE
SSP2IP
TRISC7
TRISD7
ADIF
ADIE
RCIF
RCIE
RCIP
—
TMR2IF
TMR1IF
PIE1
TMR2IE TMR1IE
TMR2IP TMR1IP
IPR1
ADIP
PIR2
CMIF
—
—
CCP2IF
CCP2IE
CCP2IP
—
PIE2
CMIE
—
—
—
IPR2
CMIP
—
—
—
—
PIR3
BCL2IF
BCL2IE
BCL2IP
TRISC6
TRISD6
—
—
—
—
PIE3
—
—
—
—
—
—
IPR3
—
—
—
—
—
—
TRISC
TRISD(1)
TRISC5
TRISD5
TRISC4
TRISD4
TRISC3
TRISD3
TRISC2
TRISD2
TRISC1
TRISD1
TRISC0
TRISD0
SSP1BUF MSSP1 Receive Buffer/Transmit Register
SSP1ADD MSSP1 Address Register (I2C™ Slave mode).
MSSP1 Baud Rate Reload Register (I2C Master mode).
SSP1CON1 WCOL
SSPOV
SSPEN
CKP
SSPM3
RCEN
SSPM2
PEN
SSPM1
RSEN
SSPM0
SEN
SEN
BF
48
48
48
48
50
50
SSP1CON2 GCEN ACKSTAT ACKDT
ACKEN
GCEN ACKSTAT ADMSK5(2) ADMSK4(2) ADMSK3(2) ADMSK2(2) ADMSK1(2)
SSP1STAT
SMP
CKE
D/A
P
S
R/W
UA
SSP2BUF MSSP2 Receive Buffer/Transmit Register
SSP2ADD MSSP2 Address Register (I2C Slave mode).
MSSP2 Baud Rate Reload Register (I2C Master mode).
SSP2CON1 WCOL
SSPOV
SSPEN
CKP
SSPM3
RCEN
SSPM2
PEN
SSPM1
RSEN
SSPM0
SEN
SEN
BF
50
50
48
50
SSP2CON2 GCEN ACKSTAT ACKDT
ACKEN
GCEN ACKSTAT ADMSK5(2) ADMSK4(2) ADMSK3(2) ADMSK2(2) ADMSK1(2)
SSP2STAT
SMP CKE D/A R/W UA
P
S
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the MSSP module in I2C™ mode.
Note 1: These registers and/or bits are not implemented on 28-pin devices and should be read as ‘0’.
2: Alternate names and definitions for these bits when the MSSP module is operating in I2C Slave mode. See
Section 16.4.3.2 “Address Masking” for details.
DS39682E-page 192
© 2009 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
