PIC18F45J10 FAMILY
FIGURE 16-24:
STOP CONDITION RECEIVE OR TRANSMIT MODE
SCLx = 1for TBRG, followed by SDAx = 1for TBRG
after SDAx sampled high. P bit (SSPxSTAT<4>) is set.
Write to SSPxCON2,
set PEN
PEN bit (SSPxCON2<2>) is cleared by
hardware and the SSPxIF bit is set
Falling edge of
9th clock
TBRG
SCLx
SDAx
ACK
P
TBRG
TBRG
TBRG
SCLx brought high after TBRG
SDAx asserted low before rising edge of clock
to set up Stop condition
Note: TBRG = one Baud Rate Generator period.
16.4.14 SLEEP OPERATION
16.4.17 MULTI-MASTER COMMUNICATION,
BUS COLLISION AND BUS
ARBITRATION
While in Sleep mode, the I2C module can receive
addresses or data and when an address match or
complete byte transfer occurs, wake the processor
from Sleep (if the MSSP interrupt is enabled).
Multi-Master mode support is achieved by bus arbitra-
tion. When the master outputs address/data bits onto
the SDAx pin, arbitration takes place when the master
outputs a ‘1’ on SDAx, by letting SDAx float high, and
another master asserts a ‘0’. When the SCLx pin floats
high, data should be stable. If the expected data on
SDAx is a ‘1’ and the data sampled on the SDAx
pin = 0, then a bus collision has taken place. The
master will set the Bus Collision Interrupt Flag, BCLxIF
and reset the I2C port to its Idle state (Figure 16-25).
16.4.15 EFFECTS OF A RESET
A Reset disables the MSSP module and terminates the
current transfer.
16.4.16 MULTI-MASTER MODE
In Multi-Master mode, the interrupt generation on the
detection of the Start and Stop conditions allows the
determination of when the bus is free. The Stop (P) and
Start (S) bits are cleared from a Reset or when the
MSSP module is disabled. Control of the I2C bus may
be taken when the P bit (SSPxSTAT<4>) is set, or the
bus is Idle, with both the S and P bits clear. When the
bus is busy, enabling the MSSP interrupt will generate
the interrupt when the Stop condition occurs.
If a transmit was in progress when the bus collision
occurred, the transmission is halted, the BF flag is
cleared, the SDAx and SCLx lines are deasserted and
the SSPxBUF can be written to. When the user services
the bus collision Interrupt Service Routine, and if the I2C
bus is free, the user can resume communication by
asserting a Start condition.
In multi-master operation, the SDAx line must be
monitored for arbitration to see if the signal level is the
expected output level. This check is performed in
hardware with the result placed in the BCLxIF bit.
If a Start, Repeated Start, Stop or Acknowledge condition
was in progress when the bus collision occurred, the
condition is aborted, the SDAx and SCLx lines are deas-
serted and the respective control bits in the SSPxCON2
register are cleared. When the user services the bus
collision Interrupt Service Routine, and if the I2C bus is
free, the user can resume communication by asserting a
Start condition.
The states where arbitration can be lost are:
• Address Transfer
• Data Transfer
• A Start Condition
The master will continue to monitor the SDAx and SCLx
pins. If a Stop condition occurs, the SSPxIF bit will be set.
• A Repeated Start Condition
• An Acknowledge Condition
A write to the SSPxBUF will start the transmission of
data at the first data bit regardless of where the
transmitter left off when the bus collision occurred.
In Multi-Master mode, the interrupt generation on the
detection of Start and Stop conditions allows the determi-
nation of when the bus is free. Control of the I2C bus can
be taken when the P bit is set in the SSPxSTAT register,
or the bus is Idle and the S and P bits are cleared.
DS39682E-page 186
© 2009 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
