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PIC18F25J10-I/SS 参数 Datasheet PDF下载

PIC18F25J10-I/SS图片预览
型号: PIC18F25J10-I/SS
PDF下载: 下载PDF文件 查看货源
内容描述: 28 /40/ 44引脚高性能, RISC微控制器 [28/40/44-Pin High-Performance, RISC Microcontrollers]
分类和应用: 微控制器和处理器外围集成电路光电二极管PC时钟
文件页数/大小: 368 页 / 5652 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC18F45J10 FAMILY  
15.4.2  
PWM DUTY CYCLE  
Note:  
If the PWM duty cycle value is longer than  
the PWM period, the CCP1 pin will not be  
cleared.  
The PWM duty cycle is specified by writing to the  
CCPR1L register and to the CCP1CON<5:4> bits. Up  
to 10-bit resolution is available. The CCPR1L register  
contains the eight MSbs and the CCP1CON<5:4>  
contains the two LSbs. This 10-bit value is represented  
by CCPR1L:CCP1CON<5:4>. The PWM duty cycle is  
calculated by the following equation:  
15.4.3  
PWM OUTPUT CONFIGURATIONS  
The P1M<1:0> bits in the CCP1CON register allow one  
of four configurations:  
• Single Output  
EQUATION 15-2:  
• Half-Bridge Output  
• Full-Bridge Output, Forward mode  
• Full-Bridge Output, Reverse mode  
PWM Duty Cycle = (CCPR1L:CCP1CON<5:4>) •  
TOSC • (TMR2 Prescale Value)  
The Single Output mode is the standard PWM mode  
discussed in Section 15.4 “Enhanced PWM Mode”.  
The Half-Bridge and Full-Bridge Output modes are  
covered in detail in the sections that follow.  
CCPR1L and CCP1CON<5:4> can be written to at any  
time, but the duty cycle value is not copied into  
CCPR1H until a match between PR2 and TMR2 occurs  
(i.e., the period is complete). In PWM mode, CCPR1H  
is a read-only register.  
The general relationship of the outputs in all  
configurations is summarized in Figure 15-2.  
The CCPR1H register and a 2-bit internal latch are  
used to double-buffer the PWM duty cycle. This  
double-buffering is essential for glitchless PWM opera-  
tion. When the CCPR1H and 2-bit latch match TMR2,  
concatenated with an internal 2-bit Q clock or two bits  
of the TMR2 prescaler, the CCP1 pin is cleared. The  
maximum PWM resolution (bits) for a given PWM  
frequency is given by the following equation:  
EQUATION 15-3:  
FOSC  
log  
(
)
FPWM  
bits  
PWM Resolution (max) =  
log(2)  
TABLE 15-2: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz  
PWM Frequency  
2.44 kHz  
9.77 kHz  
39.06 kHz 156.25 kHz 312.50 kHz 416.67 kHz  
Timer Prescaler (1, 4, 16)  
PR2 Value  
16  
FFh  
10  
4
1
1
3Fh  
8
1
1Fh  
7
1
FFh  
10  
FFh  
10  
17h  
6.58  
Maximum Resolution (bits)  
DS39682E-page 138  
© 2009 Microchip Technology Inc.