PIC18F45J10 FAMILY
FIGURE 1-1:
PIC18F24J10/25J10 (28-PIN) BLOCK DIAGRAM
Data Bus<8>
Table Pointer<21>
Data Latch
PORTA
8
8
inc/dec logic
21
RA0/AN0
RA1/AN1
Data Memory
(1 Kbyte)
PCLATH
PCLATU
RA2/AN2/VREF-/CVREF
RA3/AN3/VREF+
Address Latch
20
PCU PCH PCL
Program Counter
RA5/AN4/SS1/C2OUT
12
Data Address<12>
31 Level Stack
STKPTR
4
BSR
12
FSR0
FSR1
FSR2
4
Address Latch
Access
Bank
Program Memory
(16/32 Kbytes)
12
Data Latch
PORTB
RB0/INT0/FLT0/AN12
RB1/INT1/AN10
inc/dec
logic
8
Table Latch
RB2/INT2/AN8
RB3/AN9/CCP2(1)
RB4/KBI0/AN11
Address
Decode
ROM Latch
IR
RB5/KBI1/T0CKI/C1OUT
RB6/KBI2/PGC
RB7/KBI3/PGD
Instruction Bus <16>
8
State Machine
Control Signals
Instruction
Decode and
Control
PRODH PRODL
8 x 8 Multiply
PORTC
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2(1)
RC2/CCP1
3
8
W
BITOP
8
RC3/SCK1/SCL1
RC4/SDI1/SDA1
8
8
RC5/SDO1
RC6/TX/CK
RC7/RX/DT
VDDCORE
OSC1
Internal
Oscillator
Block
Power-up
Timer
8
8
Oscillator
Start-up Timer
ALU<8>
8
INTRC
Oscillator
OSC2
Power-on
Reset
T1OSI
T1OSO
Watchdog
Timer
Brown-out(2)
Reset
Fail-Safe
Precision
Band Gap
Reference
Single-Supply
Programming
MCLR
In-Circuit
Debugger
VDD, VSS
Clock Monitor
ADC
10-Bit
BOR(2)
Timer0
CCP1
Timer1
CCP2
Timer2
MSSP
Comparator
EUSART
Note 1: CCP2 is multiplexed with RC1 when Configuration bit, CCP2MX, is set, or RB3 when CCP2MX is not set.
2: Brown-out Reset is not available in PIC18LF2XJ10/4XJ10 devices.
DS39682E-page 10
© 2009 Microchip Technology Inc.