PIC18FXX20
TABLE 3-3:
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
MCLR Resets
WDT Reset
Power-on Reset,
Brown-out Reset
Wake-up via WDT
or Interrupt
Register
Applicable Devices
RESET Instruction
Stack Resets
PORTJ
PORTH
PORTG
PORTF
PORTE
PORTD
PORTC
PORTB
xxxx xxxx
0000 xxxx
---x xxxx
x000 0000
---- -000
xxxx xxxx
xxxx xxxx
xxxx xxxx
-x0x 0000(5)
0000 0000
1111 1111
-000 0000
xxxx xxxx
xxxx xxxx
0000 0000
xxxx xxxx
xxxx xxxx
0000 0000
0000 0000
0000 0000
0000 0000
0000 -010
0000 000x
uuuu uuuu
0000 uuuu
uuuu uuuu
u000 0000
---- -000
uuuu uuuu
uuuu uuuu
uuuu uuuu
-u0u 0000(5)
0000 0000
1111 1111
-000 0000
uuuu uuuu
uuuu uuuu
0000 0000
uuuu uuuu
uuuu uuuu
0000 0000
0000 0000
0000 0000
0000 0000
0000 -010
0000 000x
uuuu uuuu
uuuu uuuu
---u uuuu
u000 0000
---- -uuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
-uuu uuuu(5)
uuuu uuuu
uuuu uuuu
-uuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu -uuu
uuuu uuuu
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PORTA(5,6) PIC18F6X20 PIC18F8X20
TMR4
PR4
T4CON
CCPR4H
CCPR4L
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
CCP4CON PIC18F6X20 PIC18F8X20
CCPR5H
CCPR5L
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
CCP5CON PIC18F6X20 PIC18F8X20
SPBRG2
RCREG2
TXREG2
TXSTA2
RCSTA2
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
Legend: u= unchanged, x= unknown, -= unimplemented bit, read as '0', q= value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
4: See Table 3-2 for RESET value for specific condition.
5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other
Oscillator modes, they are disabled and read ‘0’.
6: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they are read ‘0’.
DS39609A-page 36
Advance Information
2003 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
