欢迎访问ic37.com |
会员登录 免费注册
发布采购

PIC18F8620-I/PT 参数 Datasheet PDF下载

PIC18F8620-I/PT图片预览
型号: PIC18F8620-I/PT
PDF下载: 下载PDF文件 查看货源
内容描述: 八十〇分之六十四引脚高性能1 Mbit的增强型闪存微控制器与A / D [64/80-Pin High Performance 1 Mbit Enhanced FLASH Microcontrollers with A/D]
分类和应用: 闪存微控制器和处理器外围集成电路PC时钟
文件页数/大小: 366 页 / 6797 K
品牌: MICROCHIP [ MICROCHIP ]
 浏览型号PIC18F8620-I/PT的Datasheet PDF文件第353页浏览型号PIC18F8620-I/PT的Datasheet PDF文件第354页浏览型号PIC18F8620-I/PT的Datasheet PDF文件第355页浏览型号PIC18F8620-I/PT的Datasheet PDF文件第356页浏览型号PIC18F8620-I/PT的Datasheet PDF文件第358页浏览型号PIC18F8620-I/PT的Datasheet PDF文件第359页浏览型号PIC18F8620-I/PT的Datasheet PDF文件第360页浏览型号PIC18F8620-I/PT的Datasheet PDF文件第361页  
PIC18FXX20  
MOVLW ............................................................................ 285  
MOVWF ........................................................................... 285  
MPLAB C17 and MPLAB C18 C Compilers ..................... 302  
MPLAB ICD In-Circuit Debugger ...................................... 303  
MPLAB ICE High Performance Universal In-Circuit  
Emulator with MPLAB IDE ....................................... 303  
MPLAB Integrated Development  
N
NEGF ............................................................................... 287  
NOP ................................................................................. 287  
O
OPCODE Field Descriptions ............................................ 260  
OPTION_REG Register  
Environment Software .............................................. 301  
MPLINK Object Linker/MPLIB Object Librarian ............... 302  
MSSP ............................................................................... 157  
ACK Pulse ........................................................ 170, 171  
Clock Stretching ....................................................... 176  
10-bit Slave Receive Mode (SEN = 1) ............. 176  
10-bit Slave Transmit Mode ............................. 176  
7-bit Slave Receive Mode (SEN = 1) ............... 176  
7-bit Slave Transmit Mode ............................... 176  
Clock Synchronization and the CKP bit  
PSA Bit .................................................................... 133  
T0CS Bit .................................................................. 133  
T0PS2:T0PS0 Bits ................................................... 133  
T0SE Bit .................................................................. 133  
Oscillator Configuration ..................................................... 21  
EC .............................................................................. 21  
ECIO .......................................................................... 21  
HS .............................................................................. 21  
HS + PLL ................................................................... 21  
LP .............................................................................. 21  
RC ............................................................................. 21  
RCIO .......................................................................... 21  
XT .............................................................................. 21  
Oscillator Selection .......................................................... 239  
Oscillator Switching Feature .............................................. 24  
Oscillator Transitions ................................................. 26  
System Clock Switch Bit ............................................ 25  
Oscillator, Timer1 ..............................................135, 137, 145  
Oscillator, Timer3 ............................................................. 143  
Oscillator, WDT ................................................................ 250  
(SEN = 1) ......................................................... 177  
Control Registers (general) ...................................... 157  
Enabling SPI I/O ...................................................... 161  
2
I C Mode .................................................................. 166  
Acknowledge Sequence Timing ....................... 190  
Baud Rate Generator ....................................... 183  
Bus Collision During a Repeated START  
Condition .................................................. 194  
Bus Collision During a START Condition ......... 192  
Bus Collision During a STOP Condition ........... 195  
Clock Arbitration ............................................... 184  
Effect of a RESET ............................................ 191  
P
2
I C Clock Rate w/BRG ..................................... 183  
Packaging ........................................................................ 343  
Details ...................................................................... 344  
Marking .................................................................... 343  
Parallel Slave Port (PSP) ..........................................111, 128  
Associated Registers ............................................... 130  
RE0/RD/AN5 Pin ..................................................... 128  
RE1/WR/AN6 Pin ..................................................... 128  
RE2/CS/AN7 Pin ...................................................... 128  
Read Waveforms ..................................................... 130  
Select (PSPMODE Bit) .....................................111, 128  
Write Waveforms ..................................................... 129  
Parallel Slave Port Requirements (PIC18F8X20) ............ 329  
PICDEM 1 Low Cost PICmicro  
Master Mode .................................................... 181  
Reception ................................................. 187  
Repeated START Timing ......................... 186  
Master Mode START Condition ....................... 185  
Master Mode Transmission .............................. 187  
Multi-Master Communication, Bus Collision  
and Arbitration ......................................... 191  
Multi-Master Mode ........................................... 191  
Registers .......................................................... 166  
SLEEP Operation ............................................. 191  
STOP Condition Timing ................................... 190  
2
2
I C Mode. See I C  
Module Operation .................................................... 170  
Operation ................................................................. 160  
Slave Mode .............................................................. 170  
Addressing ....................................................... 170  
Reception ......................................................... 171  
Transmission .................................................... 171  
SPI  
Master Mode .................................................... 162  
SPI Clock ......................................................... 162  
SPI Master Mode ..................................................... 162  
SPI Mode ................................................................. 157  
SPI Mode. See SPI  
Demonstration Board ............................................... 304  
PICDEM 17 Demonstration Board ................................... 304  
PICDEM 2 Low Cost PIC16CXX  
Demonstration Board ............................................... 304  
PICSTART Plus Entry Level Development  
Programmer ............................................................. 303  
PIE Registers ..................................................................... 95  
Pin Functions  
AVDD .......................................................................... 20  
AVSS .......................................................................... 20  
MCLR/VPP ................................................................. 11  
OSC1/CLKI ................................................................ 11  
OSC2/CLKO/RA6 ...................................................... 11  
RA0/AN0 .................................................................... 12  
RA1/AN1 .................................................................... 12  
RA2/AN2/VREF- ......................................................... 12  
RA3/AN3/VREF+ ........................................................ 12  
RA4/T0CKI ................................................................ 12  
RA5/AN4/LVDIN ........................................................ 12  
RA6 ............................................................................ 12  
RB0/INT0 ................................................................... 13  
SPI Slave Mode ....................................................... 163  
Select Synchronization .................................... 163  
SSPBUF Register .................................................... 162  
SSPSR Register ...................................................... 162  
Typical Connection .................................................. 161  
MSSP Module  
SPI Master./Slave Connection ................................. 161  
MULLW ............................................................................ 286  
MULWF ............................................................................ 286  
2003 Microchip Technology Inc.  
Advance Information  
DS39609A-page 355