PIC18FXX20
TABLE 26-22: MASTER SSP I2C BUS DATA REQUIREMENTS
Param.
Symbol
Characteristic
Min
Max Units
Conditions
No.
100
THIGH
Clock high time 100 kHz mode
400 kHz mode
2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
—
—
—
—
—
ms
ms
ms
ms
ms
ms
ns
1 MHz mode(1) 2(TOSC)(BRG + 1)
101
102
103
90
TLOW
TR
Clock low time
100 kHz mode
400 kHz mode
2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
1 MHz mode(1) 2(TOSC)(BRG + 1)
—
SDA and SCL
rise time
100 kHz mode
400 kHz mode
1 MHz mode(1)
100 kHz mode
400 kHz mode
1 MHz mode(1)
—
1000
300
300
300
300
100
—
CB is specified to be from
10 to 400 pF
20 + 0.1 CB
ns
—
—
ns
TF
SDA and SCL
fall time
ns
ns
CB is specified to be from
10 to 400 pF
20 + 0.1 CB
—
2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
ns
TSU:STA START condition 100 kHz mode
ms Only relevant for
setup time
Repeated START
condition
400 kHz mode
—
—
ms
ms
1 MHz mode(1) 2(TOSC)(BRG + 1)
91
THD:STA START condition 100 kHz mode
2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
—
—
—
—
0.9
—
—
—
—
—
—
—
3500
1000
—
—
—
ms After this period, the first
hold time
clock pulse is generated
400 kHz mode
ms
ms
ns
ms
ns
1 MHz mode(1) 2(TOSC)(BRG + 1)
106
107
92
THD:DAT Data input
hold time
100 kHz mode
400 kHz mode
1 MHz mode(1)
100 kHz mode
400 kHz mode
1 MHz mode(1)
0
0
TBD
250
100
TSU:DAT Data input
setup time
ns
(Note 2)
ns
ns
ms
ms
ms
ns
TBD
TSU:STO STOP condition 100 kHz mode
2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
setup time
400 kHz mode
1 MHz mode(1) 2(TOSC)(BRG + 1)
109
110
D102
TAA
TBUF
CB
Output validfrom 100 kHz mode
—
—
—
4.7
1.3
TBD
—
clock
400 kHz mode
1 MHz mode(1)
100 kHz mode
400 kHz mode
1 MHz mode(1)
ns
ns
Bus free time
ms Time the bus must be free
before a new transmission
can start
ms
ms
pF
—
400
Bus capacitive loading
Note 1: Maximum pin capacitance = 10 pF for all I2C pins.
2: A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but parameter #107 ≥ 250 ns
must then be met. This will automatically be the case if the device does not stretch the LOW period of the
SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to
the SDA line, parameter #102 + parameter #107 = 1000 + 250 = 1250 ns (for 100 kHz mode) before the SCL
line is released.
2003 Microchip Technology Inc.
Advance Information
DS39609A-page 337
MICROCHIP [ MICROCHIP ]
