PIC18FXX20
RETFIE
Return from Interrupt
RETLW
Return Literal to W
Syntax:
Operands:
Operation:
[ label ] RETFIE [s]
s ∈ [0,1]
Syntax:
Operands:
Operation:
[ label ] RETLW k
0 ≤ k ≤ 255
(TOS) → PC,
k → W,
1 → GIE/GIEH or PEIE/GIEL,
if s = 1
(TOS) → PC,
PCLATU, PCLATH are unchanged
(WS) → W,
Status Affected:
Encoding:
Description:
None
(STATUSS) → STATUS,
(BSRS) → BSR,
0000
1100
kkkk
kkkk
PCLATU, PCLATH are unchanged.
W is loaded with the eight-bit literal
'k'. The program counter is loaded
from the top of the stack (the return
address). The high address latch
(PCLATH) remains unchanged.
1
2
Status Affected:
Encoding:
Description:
GIE/GIEH, PEIE/GIEL.
0000
0000
0001
000s
Return from Interrupt. Stack is
popped and Top-of-Stack (TOS) is
loaded into the PC. Interrupts are
enabled by setting either the high
or low priority global interrupt
enable bit. If ‘s’ = 1, the contents of
the shadow registers WS,
STATUSS and BSRS are loaded
into their corresponding registers,
W, STATUS and BSR. If ‘s’ = 0, no
update of these registers occurs
(default).
Words:
Cycles:
Q Cycle Activity:
Q1
Q2
Q3
Q4
pop PC from
stack, Write
to W
No
operation
Decode
Read
Process
literal 'k'
Data
No
No
operation
No
operation
operation
Words:
Cycles:
1
2
Example:
CALL TABLE ; W contains table
; offset value
Q Cycle Activity:
Q1
Q2
Q3
Q4
; W now has
; table value
Decode
No
No
pop PC from
:
operation
operation
stack
Set GIEH or
GIEL
No
operation
TABLE
ADDWF PCL ; W = offset
RETLW k0
RETLW k1
:
; Begin table
;
No
No
No
operation
operation
operation
:
RETLW kn
; End of table
RETFIE
1
Example:
After Interrupt
Before Instruction
PC
=
=
=
=
=
TOS
WS
W
W
=
0x07
BSR
STATUS
BSRS
STATUSS
1
After Instruction
GIE/GIEH, PEIE/GIEL
W
=
value of kn
DS39609A-page 290
Advance Information
2003 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
