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PIC18F8620-I/PT 参数 Datasheet PDF下载

PIC18F8620-I/PT图片预览
型号: PIC18F8620-I/PT
PDF下载: 下载PDF文件 查看货源
内容描述: 八十〇分之六十四引脚高性能1 Mbit的增强型闪存微控制器与A / D [64/80-Pin High Performance 1 Mbit Enhanced FLASH Microcontrollers with A/D]
分类和应用: 闪存微控制器和处理器外围集成电路PC时钟
文件页数/大小: 366 页 / 6797 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC18FXX20  
21.1 Configuring the Comparator  
21.0 COMPARATOR VOLTAGE  
REFERENCE MODULE  
Voltage Reference  
The Comparator Voltage Reference can output 16 dis-  
tinct voltage levels for each range. The equations used  
to calculate the output of the Comparator Voltage  
Reference are as follows:  
The Comparator Voltage Reference is a 16-tap resistor  
ladder network that provides a selectable voltage refer-  
ence. The resistor ladder is segmented to provide two  
ranges of CVREF values and has a power-down func-  
tion to conserve power when the reference is not being  
used. The CVRCON register controls the operation of  
the reference as shown in Register 21-1. The block  
diagram is given in Figure 21-1.  
The comparator reference supply voltage can come  
from either VDD or VSS, or the external VREF+ and  
VREF- that are multiplexed with RA3 and RA2. The  
comparator reference supply voltage is controlled by  
the CVRSS bit.  
If CVRR = 1:  
CVREF= (CVR<3:0>/24) x CVRSRC  
If CVRR = 0:  
CVREF = (CVDD x 1/4) + (CVR<3:0>/32) x CVRSRC  
The settling time of the Comparator Voltage Reference  
must be considered when changing the CVREF output  
(Section 26.0).  
Note:  
In order to select external VREF+ and VREF-  
supply voltages, the Voltage Reference  
Configuration bits (VCFG1:VCFG0) of the  
ADCON1 register must be set appropriately.  
REGISTER 21-1:  
CVRCON REGISTER  
R/W-0  
CVREN  
R/W-0  
CVROE  
R/W-0  
CVRR  
R/W-0  
CVRSS  
R/W-0  
CVR3  
R/W-0  
CVR2  
R/W-0  
CVR1  
R/W-0  
CVR0  
bit 7  
bit 0  
bit 7  
bit 6  
bit 5  
bit 4  
bit 3-0  
CVREN: Comparator Voltage Reference Enable bit  
1= CVREF circuit powered on  
0= CVREF circuit powered down  
CVROE: Comparator VREF Output Enable bit(1)  
1= CVREF voltage level is also output on the RF5/AN10/CVREF pin  
0= CVREF voltage is disconnected from the RF5/AN10/CVREF pin  
CVRR: Comparator VREF Range Selection bit  
1= 0.00 CVRSRC to 0.75 CVRSRC, with CVRSRC/24 step size  
0= 0.25 CVRSRC to 0.75 CVRSRC, with CVRSRC/32 step size  
CVRSS: Comparator VREF Source Selection bit(2)  
1= Comparator reference source CVRSRC = VREF+ – VREF-  
0= Comparator reference source CVRSRC = VDD – VSS  
CVR3:CVR0: Comparator VREF Value Selection bits (0 VR3:VR0 15)  
When CVRR = 1:  
CVREF = (CVR<3:0>/ 24) (CVRSRC)  
When CVRR = 0:  
CVREF = 1/4 (CVRSRC) + (CVR3:CVR0/ 32) (CVRSRC)  
Note 1: If enabled for output, RF5 must also be configured as an input by setting TRISF<5>  
to ‘1’.  
2: In order to select external VREF+ and VREF- supply voltages, the Voltage Refer-  
ence Configuration bits (VCFG1:VCFG0) of the ADCON1 register must be set  
appropriately.  
Legend:  
R = Readable bit  
- n = Value at POR  
W = Writable bit  
‘1’ = Bit is set  
U = Unimplemented bit, read as ‘0’  
‘0’ = Bit is cleared x = Bit is unknown  
2003 Microchip Technology Inc.  
Advance Information  
DS39609A-page 229  
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