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PIC18F8620-I/PT 参数 Datasheet PDF下载

PIC18F8620-I/PT图片预览
型号: PIC18F8620-I/PT
PDF下载: 下载PDF文件 查看货源
内容描述: 八十〇分之六十四引脚高性能1 Mbit的增强型闪存微控制器与A / D [64/80-Pin High Performance 1 Mbit Enhanced FLASH Microcontrollers with A/D]
分类和应用: 闪存微控制器和处理器外围集成电路PC时钟
文件页数/大小: 366 页 / 6797 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC18FXX20  
TABLE 1-2:  
Pin Name  
PIC18FXX20 PINOUT I/O DESCRIPTIONS (CONTINUED)  
Pin Number  
Pin  
Buffer  
Type  
Description  
Type  
PIC18F6X20 PIC18F8X20  
PORTD is a bi-directional I/O port. These  
pins have TTL input buffers when external  
memory is enabled.  
RD0/PSP0/AD0  
RD0  
58  
55  
54  
53  
52  
51  
50  
49  
72  
69  
68  
67  
66  
65  
64  
63  
I/O  
I/O  
I/O  
ST  
Digital I/O.  
PSP0  
TTL  
TTL  
Parallel Slave Port data.  
External memory address/data 0.  
AD0(3)  
RD1/PSP1/AD1  
RD1  
I/O  
I/O  
I/O  
ST  
TTL  
TTL  
Digital I/O.  
Parallel Slave Port data.  
External memory address/data 1.  
PSP1  
AD1(3)  
RD2/PSP2/AD2  
RD2  
I/O  
I/O  
I/O  
ST  
TTL  
TTL  
Digital I/O.  
Parallel Slave Port data.  
External memory address/data 2.  
PSP2  
AD2(3)  
RD3/PSP3/AD3  
RD3  
I/O  
I/O  
I/O  
ST  
TTL  
TTL  
Digital I/O.  
Parallel Slave Port data.  
External memory address/data 3.  
PSP3  
AD3(3)  
RD4/PSP4/AD4  
RD4  
I/O  
I/O  
I/O  
ST  
TTL  
TTL  
Digital I/O.  
Parallel Slave Port data.  
External memory address/data 4.  
PSP4  
AD4(3)  
RD5/PSP5/AD5  
RD5  
I/O  
I/O  
I/O  
ST  
TTL  
TTL  
Digital I/O.  
Parallel Slave Port data.  
External memory address/data 5.  
PSP5  
AD5(3)  
RD6/PSP6/AD6  
RD6  
I/O  
I/O  
I/O  
ST  
TTL  
TTL  
Digital I/O.  
Parallel Slave Port data.  
External memory address/data 6.  
PSP6  
AD6(3)  
RD7/PSP7/AD7  
RD7  
I/O  
I/O  
I/O  
ST  
Digital I/O.  
PSP7  
TTL  
Parallel Slave Port data.  
AD7(3)  
TTL  
External memory address/data 7.  
Legend: TTL = TTL compatible input  
CMOS = CMOS compatible input or output  
Analog = Analog input  
ST = Schmitt Trigger input with CMOS levels  
I
= Input  
= Power  
O
= Output  
P
OD  
= Open Drain (no P diode to VDD)  
Note 1: Alternate assignment for CCP2 when CCP2MX is not selected (all Operating modes except  
Microcontroller).  
2: Default assignment when CCP2MX is set.  
3: External memory interface functions are only available on PIC18F8X20 devices.  
4: CCP2 is multiplexed with this pin by default when configured in Microcontroller mode. Otherwise, it is  
multiplexed with either RB3 or RC1.  
5: PORTH and PORTJ are only available on PIC18F8X20 (80-pin) devices.  
6: AVDD must be connected to a positive supply and AVSS must be connected to a ground reference for proper  
operation of the part in User or ICSP modes. See parameter D001A for details.  
2003 Microchip Technology Inc.  
Advance Information  
DS39609A-page 15  
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