PIC18FXX20
make a pin an input. The user should refer to the corre-
sponding peripheral section for the correct TRIS bit
settings.
10.7 PORTG, TRISG and LATG
Registers
PORTG is a 5-bit wide, bi-directional port. The corre-
sponding data direction register is TRISG. Setting a
TRISG bit (= 1) will make the corresponding PORTG
pin an input (i.e., put the corresponding output driver in
a High-Impedance mode). Clearing a TRISG bit (= 0)
will make the corresponding PORTC pin an output (i.e.,
put the contents of the output latch on the selected pin).
Note: On a Power-on Reset, these pins are
configured as digital inputs.
The pin override value is not loaded into the TRIS reg-
ister. This allows read-modify-write of the TRIS register,
without concern due to peripheral overrides.
EXAMPLE 10-7:
INITIALIZING PORTG
The Data Latch register (LATG) is also memory
mapped. Read-modify-write operations on the LATG
register, read and write the latched output value for
PORTG.
PORTG is multiplexed with both CCP and USART
functions (Table 10-13). PORTG pins have Schmitt
Trigger input buffers.
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTG pin. Some
peripherals override the TRIS bit to make a pin an out-
put, while other peripherals override the TRIS bit to
CLRF
PORTG
; Initialize PORTG by
; clearing output
; data latches
CLRF
LATG
; Alternate method
; to clear output
; data latches
; Value used to
; initialize data
; direction
; Set RG1:RG0 as outputs
; RG2 as input
; RG4:RG3 as inputs
MOVLW
MOVWF
0x04
TRISG
FIGURE 10-16:
PORTG BLOCK DIAGRAM (PERIPHERAL OUTPUT OVERRIDE)
PORTG/Peripheral Out Select
Peripheral Data Out
VDD
P
0
1
RD LATG
Data Bus
D
Q
Q
(1)
I/O pin
WR LATG or
WR PORTG
CK
Data Latch
N
D
Q
VSS
TRIS
Override
Logic
WR TRISG
Q
CK
TRIS Latch
RD TRISG
Schmitt
Trigger
Peripheral Output
TRIS OVERRIDE
(2)
Enable
Pin
Override
Peripheral
Q
D
RG0
RG1
Yes
Yes
CCP3 I/O
USART1 Async
Xmit, Sync Clock
USART1 Async
Rcv, Sync Data
Out
EN
RD PORTG
Peripheral Data In
RG2
Yes
RG3
RG4
Yes
Yes
CCP4 I/O
CCP5 I/O
Note 1: I/O pins have diode protection to VDD and VSS.
2: Peripheral Output Enable is only active if Peripheral Select is active.
DS39609A-page 120
Advance Information
2003 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
