PIC18FXX20
FIGURE 1-2:
PIC18F8X20 BLOCK DIAGRAM
Data Bus<8>
PORTA
PORTB
RA0/AN0
RA1/AN1
RA2/AN2/VREF-
RA3/AN3/VREF+
RA4/T0CKI
RA5/AN4/SS/LVDIN
RA6
Table Pointer<21>
inc/dec logic
Data Latch
21
8
8
Data RAM
21
Address Latch
12
21
PCLATU
PCLATH
RB0/INT0
RB1/INT1
Address<12>
RB2/INT2
PCU PCH PCL
Program Counter
RB3/INT3/CCP2
RB4/KBI0
RB5/KBI1/PGM
RB6/KBI2/PGC
RB7/KBI3/PGD
4
12
FSR0
4
BSR
Bank0, F
Address Latch
FSR1
FSR2
31 Level Stack
Program Memory
12
Data Latch
PORTC
RC0/T1OSO/T13CKI
RC1/T1OSI/CCP2
RC2/CCP1
inc/dec
logic
Decode
TABLELATCH
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
8
16
ROMLATCH
IR
RC6/TX1/CK1
RC7/RX1/DT1
AD15:AD0, A19:A16(1)
PORTD
PORTE
RD7/PSP7:RD0/PSP0
8
PRODH PRODL
8 x 8 Multiply
RE0/RD
RE1/WR
RE2/CS
RE3
Instruction
Decode &
Control
8
3
RE4
WREG
8
BITOP
8
8
Power-up
RE5
OSC2/CLKO
OSC1/CLKI
Timer
RE6
RE7/CCP2
Timing
Oscillator
8
Generation
PORTF
PORTG
Start-up Timer
RF0/AN5
ALU<8>
Power-on
RF1/AN6/C2OUT
RF2/AN7/C1OUT
RF3/AN8
Reset
8
Watchdog
Timer
RF4/AN9
Precision
Bandgap
Reference
Brown-out
RF5/AN10/CVREF
RF6/AN11
Reset
RF7/SS
RG0/CCP3
MCLR
VDD, VSS
RG1/TX2/CK2
RG2/RX2/DT2
RG3/CCP4
RG4/CCP5
PORTH
PORTJ
RH3:RH0
RH7/AN15:RH4/AN12
Synchronous
Serial Port
Data
USART2
USART1
EEPROM
RJ0/ALE
RJ1/OE
RJ2/WRL
BOR
LVD
Timer2
CCP3
Timer3
Timer4
CCP5
Timer0
Timer1
RJ3/WRH
RJ4/BA0
RJ5/CE
RJ6/LB
RJ7/UB
10-bit
A/D
Comparator
CCP1
CCP2
CCP4
Note 1: External memory interface pins are physically multiplexed with PORTD (AD7:AD0), PORTE (AD15:AD8) and PORTH (A19:A16).
DS39609A-page 10
AdvanceInformation
2003 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
