PIC18FXX20
FIGURE 10-9:
PORTD BLOCK DIAGRAM
IN I/O PORT MODE
10.4 PORTD, TRISD and LATD
Registers
PORTD is an 8-bit wide, bi-directional port. The corre-
sponding Data Direction register is TRISD. Setting a
TRISD bit (= 1) will make the corresponding PORTD
pin an input (i.e., put the corresponding output driver in
a High-Impedance mode). Clearing a TRISD bit (= 0)
will make the corresponding PORTD pin an output (i.e.,
put the contents of the output latch on the selected pin).
The Data Latch register (LATD) is also memory
mapped. Read-modify-write operations on the LATD
register, read and write the latched output value for
PORTD.
RD LATD
Data
Bus
D
Q
WR LATD
I/O pin(1)
or
PORTD
CK
Data Latch
D
Q
Schmitt
Trigger
Input
WR TRISD
RD TRISD
CK
TRIS Latch
Buffer
PORTD is an 8-bit port with Schmitt Trigger input buff-
ers. Each pin is individually configurable as an input or
output.
Note: On a Power-on Reset, these pins are
configured as digital inputs.
Q
D
PORTD is multiplexed with the system bus as the
external memory interface; I/O port functions are only
available when the system bus is disabled, by setting
the EBDIS bit in the MEMCOM register
(MEMCON<7>). When operating as the external mem-
ory interface, PORTD is the low order byte of the
multiplexed address/data bus (AD7:AD0).
EN
EN
RD PORTD
Note 1: I/O pins have diode protection to VDD and VSS.
PORTD can also be configured as an 8-bit wide micro-
processor port (Parallel Slave Port) by setting control
bit PSPMODE (TRISE<4>). In this mode, the input
buffers are TTL. See Section 10.10 for additional
information on the Parallel Slave Port (PSP).
EXAMPLE 10-4:
INITIALIZING PORTD
CLRF
PORTD ; Initialize PORTD by
; clearing output
; data latches
CLRF
LATD
; Alternate method
; to clear output
; data latches
MOVLW 0xCF
; Value used to
; initialize data
; direction
MOVWF TRISD
; Set RD<3:0> as inputs
; RD<5:4> as outputs
; RD<7:6> as inputs
2003 Microchip Technology Inc.
Advance Information
DS39609A-page 111
MICROCHIP [ MICROCHIP ]
