PIC18FXX20
A mismatch condition will continue to set flag bit, RBIF.
Reading PORTB will end the mismatch condition and
allow flag bit RBIF to be cleared.
The interrupt-on-change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt-on-change
feature. Polling of PORTB is not recommended while
using the interrupt-on-change feature.
For PIC18F8X20 devices, RB3 can be configured by
the configuration bit CCP2MX, as the alternate periph-
eral pin for the CCP2 module. This is only available
when the device is configured in Microprocessor,
Microprocessor with Boot Block, or Extended
Microcontroller operating modes.
10.2 PORTB, TRISB and LATB
Registers
PORTB is an 8-bit wide, bi-directional port. The corre-
sponding Data Direction register is TRISB. Setting a
TRISB bit (= 1) will make the corresponding PORTB
pin an input (i.e., put the corresponding output driver in
a High-Impedance mode). Clearing a TRISB bit (= 0)
will make the corresponding PORTB pin an output (i.e.,
put the contents of the output latch on the selected pin).
The Data Latch register (LATB) is also memory
mapped. Read-modify-write operations on the LATB
register, read and write the latched output value for
PORTB.
The RB5 pin is used as the LVP programming pin.
When the LVP configuration bit is programmed, this pin
loses the I/O function and become a programming test
function.
EXAMPLE 10-2:
INITIALIZING PORTB
; Initialize PORTB by
; clearing output
; data latches
CLRF
PORTB
CLRF
LATB
; Alternate method
; to clear output
; data latches
Note: When LVP is enabled, the weak pull-up on
RB5 is disabled.
MOVLW 0xCF
; Value used to
; initialize data
; direction
; Set RB<3:0> as inputs
; RB<5:4> as outputs
; RB<7:6> as inputs
FIGURE 10-5:
BLOCK DIAGRAM OF
RB7:RB4 PINS
MOVWF TRISB
VDD
RBPU(2)
Data Bus
Weak
P
Pull-up
Each of the PORTB pins has a weak internal pull-up. A
single control bit can turn on all the pull-ups. This is per-
formed by clearing bit RBPU (INTCON2<7>). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are
disabled on a Power-on Reset.
Data Latch
D
Q
WR LATB
or PORTB
I/O pin(1)
CK
TRIS Latch
D
Q
Note: On a Power-on Reset, these pins are
WR TRISB
TTL
CK
configured as digital inputs.
Input
Buffer
ST
Buffer
Four of the PORTB pins (RB3:RB0) are the external
interrupt pins, INT3 through INT0. In order to use these
pins as external interrupts, the corresponding TRISB
bit must be set to ‘1’.
RD TRISB
RD LATB
The other four PORTB pins (RB7:RB4) have an inter-
rupt-on-change feature. Only pins configured as inputs
can cause this interrupt to occur (i.e., any RB7:RB4 pin
configured as an output is excluded from the inter-
rupt-on-change comparison). The input pins (of
RB7:RB4) are compared with the old value latched on
the last read of PORTB. The “mismatch” outputs of
RB7:RB4 are OR’ed together to generate the RB Port
Change Interrupt with flag bit, RBIF (INTCON<0>).
Latch
Q
D
RD PORTB
Set RBIF
Q1
EN
Q
D
RD PORTB
Q3
From other
EN
RB7:RB4 pins
RB7:RB5 in Serial Programming Mode
This interrupt can wake the device from SLEEP. The
user, in the Interrupt Service Routine, can clear the
interrupt in the following manner:
a) Any read or write of PORTB (except with the
MOVFF instruction). This will end the mismatch
condition.
Note 1: I/O pins have diode protection to VDD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS bit(s)
and clear the RBPU bit (INTCON2<7>).
b) Clear flag bit RBIF.
DS39609A-page 106
Advance Information
2003 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
