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PIC18LF6720-I/PT 参数 Datasheet PDF下载

PIC18LF6720-I/PT图片预览
型号: PIC18LF6720-I/PT
PDF下载: 下载PDF文件 查看货源
内容描述: 八十〇分之六十四引脚高性能1 Mbit的增强型闪存微控制器与A / D [64/80-Pin High Performance 1 Mbit Enhanced FLASH Microcontrollers with A/D]
分类和应用: 闪存微控制器
文件页数/大小: 366 页 / 6797 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC18FXX20  
8.2  
Operation  
8.0  
8.1  
8 X 8 HARDWARE MULTIPLIER  
Introduction  
Example 8-1 shows the sequence to do an 8 x 8  
unsigned multiply. Only one instruction is required  
when one argument of the multiply is already loaded in  
the WREG register.  
Example 8-2 shows the sequence to do an 8 x 8 signed  
multiply. To account for the sign bits of the arguments,  
each argument’s Most Significant bit (MSb) is tested  
and the appropriate subtractions are done.  
An 8 x 8 hardware multiplier is included in the ALU of  
the PIC18FXX20 devices. By making the multiply a  
hardware operation, it completes in a single instruction  
cycle. This is an unsigned multiply that gives a 16-bit  
result. The result is stored in the 16-bit product register  
pair (PRODH:PRODL). The multiplier does not affect  
any flags in the ALUSTA register.  
Making the 8 x 8 multiplier execute in a single cycle  
gives the following advantages:  
• Higher computational throughput  
• Reduces code size requirements for multiply  
algorithms  
EXAMPLE 8-1:  
8 x 8 UNSIGNED  
MULTIPLY ROUTINE  
MOVF  
ARG1, W  
ARG2  
;
MULWF  
; ARG1 * ARG2 ->  
;
PRODH:PRODL  
The performance increase allows the device to be used  
in applications previously reserved for Digital Signal  
Processors.  
Table 8-1 shows a performance comparison between  
enhanced devices using the single cycle hardware mul-  
tiply, and performing the same function without the  
hardware multiply.  
EXAMPLE 8-2:  
8 x 8 SIGNED MULTIPLY  
ROUTINE  
MOVF  
MULWF  
ARG1,  
ARG2  
W
; ARG1 * ARG2 ->  
; PRODH:PRODL  
; Test Sign Bit  
; PRODH = PRODH  
BTFSC  
SUBWF  
ARG2, SB  
PRODH, F  
;
- ARG1  
MOVF  
ARG2,  
W
BTFSC  
SUBWF  
ARG1, SB  
PRODH, F  
; Test Sign Bit  
; PRODH = PRODH  
;
- ARG2  
TABLE 8-1:  
Routine  
PERFORMANCE COMPARISON  
Program  
Time  
@ 40 MHz @ 10 MHz @ 4 MHz  
Cycles  
Multiply Method  
Memory  
(Words)  
(Max)  
Without hardware multiply  
Hardware multiply  
Without hardware multiply  
Hardware multiply  
Without hardware multiply  
Hardware multiply  
Without hardware multiply  
Hardware multiply  
13  
1
33  
6
21  
28  
52  
35  
69  
1
91  
6
242  
28  
254  
40  
6.9 µs  
100 ns  
9.1 µs  
600 ns  
24.2 µs  
2.8 µs  
25.4 µs  
4.0 µs  
27.6 µs  
400 ns  
36.4 µs  
2.4 µs  
96.8 µs  
11.2 µs  
102.6 µs  
16.0 µs  
69 µs  
1 µs  
91 µs  
6 µs  
242 µs  
28 µs  
254 µs  
40 µs  
8 x 8 unsigned  
8 x 8 signed  
16 x 16 unsigned  
16 x 16 signed  
2003 Microchip Technology Inc.  
Advance Information  
DS39609A-page 85  
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