PIC18FXX20
TABLE 24-2: PIC18FXXX INSTRUCTION SET
16-Bit Instruction Word
MSb LSb
Mnemonic,
Operands
Status
Affected
Description
Cycles
Notes
BYTE-ORIENTED FILE REGISTER OPERATIONS
ADDWF
ADDWFC
ANDWF
CLRF
f, d, a Add WREG and f
1
1
1
1
1
0010 01da0 ffff
ffff C, DC, Z, OV, N 1, 2
ffff C, DC, Z, OV, N 1, 2
f, d, a Add WREG and Carry bit to f
f, d, a AND WREG with f
0010 0da
0001 01da
0110 101a
0001 11da
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff Z, N
ffff
1,2
2
f, a
Clear f
Z
COMF
f, d, a Complement f
ffff Z, N
ffff None
ffff None
ffff None
1, 2
4
CPFSEQ
CPFSGT
CPFSLT
DECF
DECFSZ
DCFSNZ
INCF
f, a
f, a
f, a
Compare f with WREG, skip =
Compare f with WREG, skip >
Compare f with WREG, skip <
1 (2 or 3) 0110 001a
1 (2 or 3) 0110 010a
1 (2 or 3) 0110 000a
4
1, 2
f, d, a Decrement f
1
0000 01da
ffff C, DC, Z, OV, N 1, 2, 3, 4
f, d, a Decrement f, Skip if 0
f, d, a Decrement f, Skip if Not 0
f, d, a Increment f
f, d, a Increment f, Skip if 0
f, d, a Increment f, Skip if Not 0
f, d, a Inclusive OR WREG with f
f, d, a Move f
1 (2 or 3) 0010 11da
1 (2 or 3) 0100 11da
ffff None
ffff None
1, 2, 3, 4
1, 2
1
0010 10da
ffff C, DC, Z, OV, N 1, 2, 3, 4
INCFSZ
INFSNZ
IORWF
MOVF
1 (2 or 3) 0011 11da
1 (2 or 3) 0100 10da
ffff None
ffff None
ffff Z, N
ffff Z, N
ffff None
ffff
4
1, 2
1, 2
1
1
1
2
0001 00da
0101 00da
1100 ffff
1111 ffff
0110 111a
0000 001a
0110 110a
0011 01da
0100 01da
0011 00da
0100 00da
0110 100a
0101 01da
MOVFF
f , f
Move f (source) to 1st word
s
s
d
f (destination)2nd word
d
MOVWF
MULWF
NEGF
f, a
f, a
f, a
Move WREG to f
1
1
1
1
1
1
1
1
1
ffff None
ffff None
ffff C, DC, Z, OV, N 1, 2
ffff C, Z, N
Multiply WREG with f
Negate f
RLCF
f, d, a Rotate Left f through Carry
f, d, a Rotate Left f (No Carry)
f, d, a Rotate Right f through Carry
f, d, a Rotate Right f (No Carry)
RLNCF
RRCF
ffff Z, N
ffff C, Z, N
ffff Z, N
ffff None
1, 2
RRNCF
SETF
f, a
Set f
SUBFWB
f, d, a Subtract f from WREG with
borrow
ffff C, DC, Z, OV, N 1, 2
SUBWF
SUBWFB
f, d, a Subtract WREG from f
f, d, a Subtract WREG from f with
borrow
1
1
0101 11da
0101 10da
ffff
ffff
ffff C, DC, Z, OV, N
ffff C, DC, Z, OV, N 1, 2
SWAPF
TSTFSZ
XORWF
f, d, a Swap nibbles in f
1
0011 10da
ffff
ffff
ffff
ffff None
ffff None
ffff Z, N
4
1, 2
f, a
Test f, skip if 0
1 (2 or 3) 0110 011a
f, d, a Exclusive OR WREG with f
1
0001 10da
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF
f, b, a Bit Clear f
1
1
1001 bbba
1000 bbba
ffff
ffff
ffff
ffff
ffff
ffff None
ffff None
ffff None
ffff None
ffff None
1, 2
1, 2
3, 4
3, 4
1, 2
BSF
f, b, a Bit Set f
BTFSC
BTFSS
BTG
f, b, a Bit Test f, Skip if Clear
f, b, a Bit Test f, Skip if Set
f, d, a Bit Toggle f
1 (2 or 3) 1011 bbba
1 (2 or 3) 1010 bbba
1
0111 bbba
Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value
present on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is driven low by an
external device, the data will be written back with a '0'.
2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if
assigned.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is
executed as a NOP.
4: Some instructions are 2-word instructions. The second word of these instructions will be executed as a NOP, unless the
first word of the instruction retrieves the information embedded in these 16-bits. This ensures that all program memory
locations have a valid instruction.
5: If the Table Write starts the write cycle to internal memory, the write will continue until terminated.
DS39609A-page 262
Advance Information
2003 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
