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PIC18LF6720-I/PT 参数 Datasheet PDF下载

PIC18LF6720-I/PT图片预览
型号: PIC18LF6720-I/PT
PDF下载: 下载PDF文件 查看货源
内容描述: 八十〇分之六十四引脚高性能1 Mbit的增强型闪存微控制器与A / D [64/80-Pin High Performance 1 Mbit Enhanced FLASH Microcontrollers with A/D]
分类和应用: 闪存微控制器
文件页数/大小: 366 页 / 6797 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC18FXX20  
Example 18-1 shows the calculation of the baud rate  
error for the following conditions:  
• FOSC = 16 MHz  
• Desired Baud Rate = 9600  
• BRGH = 0  
18.1 USART Baud Rate Generator  
(BRG)  
The BRG supports both the Asynchronous and Syn-  
chronous modes of the USARTs. It is a dedicated 8-bit  
baud rate generator. The SPBRG register controls the  
period of a free running 8-bit timer. In Asynchronous  
mode, bit BRGH (TXSTAx<2>) also controls the baud  
rate. In Synchronous mode, bit BRGH is ignored.  
Table 18-1 shows the formula for computation of the  
baud rate for different USART modes, which only apply  
in Master mode (internal clock).  
Given the desired baud rate and FOSC, the nearest  
integer value for the SPBRGx register can be calcu-  
lated using the formula in Table 18-1. From this, the  
error in baud rate can be determined.  
• SYNC = 0  
It may be advantageous to use the high baud rate  
(BRGH = 1), even for slower baud clocks. This is  
because the equation in Example 18-1 can reduce the  
baud rate error in some cases.  
Writing a new value to the SPBRGx register causes the  
BRG timer to be reset (or cleared). This ensures the  
BRG does not wait for a timer overflow before  
outputting the new baud rate.  
18.1.1  
SAMPLING  
The data on the RXx pin (either RC7/RX1/DT1 or  
RG2/RX2/DT2) is sampled three times by a majority  
detect circuit to determine if a high or a low level is  
present at the pin.  
EXAMPLE 18-1:  
Desired Baud Rate  
CALCULATING BAUD RATE ERROR  
=
FOSC / (64 (X + 1))  
Solving for X:  
X
X
X
=
=
=
( (FOSC / Desired Baud Rate) / 64 ) – 1  
((16000000 / 9600) / 64) – 1  
[25.042] = 25  
Calculated Baud Rate  
=
=
16000000 / (64 (25 + 1))  
9615  
Error  
=
(Calculated Baud Rate - Desired Baud Rate)  
Desired Baud Rate  
(9615 – 9600) / 9600  
0.16%  
=
=
TABLE 18-1: BAUD RATE FORMULA  
SYNC  
BRGH = 0 (Low Speed)  
BRGH = 1 (High Speed)  
0
1
(Asynchronous) Baud Rate = FOSC/(64(X+1))  
(Synchronous) Baud Rate = FOSC/(4(X+1))  
Baud Rate = FOSC/(16(X+1))  
N/A  
Legend: X = value in SPBRGx (0 to 255)  
TABLE 18-2: REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR  
Value on  
all other  
RESETS  
Value on  
Name  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
POR, BOR  
TXSTAx  
RCSTAx  
CSRC  
SPEN  
TX9  
RX9  
TXEN SYNC  
BRGH TRMT TX9D 0000 -010  
0000 -010  
0000 000x  
0000 0000  
SREN CREN ADDEN FERR OERR RX9D 0000 000x  
SPBRGx Baud Rate Generator Register  
0000 0000  
Legend: x= unknown, - = unimplemented, read as '0'. Shaded cells are not used by the BRG.  
Note: Register names generically refer to both of the identically named registers for the two USART modules, where  
‘x’ indicates the particular module. Bit names and RESET values are identical between modules.  
DS39609A-page 200  
Advance Information  
2003 Microchip Technology Inc.  
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