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PIC18LF6720-I/PT 参数 Datasheet PDF下载

PIC18LF6720-I/PT图片预览
型号: PIC18LF6720-I/PT
PDF下载: 下载PDF文件 查看货源
内容描述: 八十〇分之六十四引脚高性能1 Mbit的增强型闪存微控制器与A / D [64/80-Pin High Performance 1 Mbit Enhanced FLASH Microcontrollers with A/D]
分类和应用: 闪存微控制器
文件页数/大小: 366 页 / 6797 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC18FXX20  
If the SDA pin is sampled low during this count, the  
BRG is reset and the SDA line is asserted early  
(Figure 17-28). If, however, a '1' is sampled on the SDA  
pin, the SDA pin is asserted low at the end of the BRG  
count. The baud rate generator is then reloaded and  
counts down to ‘0’, and during this time, if the SCL pins  
are sampled as '0', a bus collision does not occur. At  
the end of the BRG count, the SCLpin is asserted low.  
17.4.17.1 Bus Collision During a START  
Condition  
During a START condition, a bus collision occurs if:  
a) SDA or SCL are sampled low at the beginning of  
the START condition (Figure 17-26).  
b) SCL is sampled low before SDA is asserted low  
(Figure 17-27).  
During a START condition, both the SDA and the SCL  
pins are monitored.  
If the SDA pin is already low, or the SCL pin is already  
low, then all of the following occur:  
• the START condition is aborted,  
• the BCLIF flag is set, and  
Note: The reason that bus collision is not a factor  
during a START condition is that no two  
bus masters can assert a START condition  
at the exact same time. Therefore, one  
master will always assert SDA before the  
other. This condition does not cause a bus  
collision, because the two masters must be  
allowed to arbitrate the first address follow-  
ing the START condition. If the address is  
the same, arbitration must be allowed to  
continue into the data portion, Repeated  
START or STOP conditions.  
the MSSP module is reset to its IDLE state  
(Figure 17-26).  
The START condition begins with the SDA and SCL  
pins de-asserted. When the SDA pin is sampled high,  
the baud rate generator is loaded from SSPADD<6:0>  
and counts down to ‘0’. If the SCL pin is sampled low  
while SDA is high, a bus collision occurs, because it is  
assumed that another master is attempting to drive a  
data '1' during the START condition.  
FIGURE 17-26:  
BUS COLLISION DURING START CONDITION (SDA ONLY)  
SDA goes low before the SEN bit is set.  
Set BCLIF,  
S bit and SSPIF set because  
SDA = 0, SCL = 1.  
SDA  
SCL  
SEN  
Set SEN, enable START  
condition if SDA = 1, SCL = 1  
SEN cleared automatically because of bus collision.  
SSP module reset into IDLE state.  
SDA sampled low before  
START condition.  
Set BCLIF.  
S bit and SSPIF set because  
BCLIF  
SDA = 0, SCL = 1.  
SSPIF and BCLIF are  
cleared in software  
S
SSPIF  
SSPIF and BCLIF are  
cleared in software  
DS39609A-page 192  
Advance Information  
2003 Microchip Technology Inc.  
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