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PIC18LF6720-I/PT 参数 Datasheet PDF下载

PIC18LF6720-I/PT图片预览
型号: PIC18LF6720-I/PT
PDF下载: 下载PDF文件 查看货源
内容描述: 八十〇分之六十四引脚高性能1 Mbit的增强型闪存微控制器与A / D [64/80-Pin High Performance 1 Mbit Enhanced FLASH Microcontrollers with A/D]
分类和应用: 闪存微控制器
文件页数/大小: 366 页 / 6797 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC18FXX20  
16.3.2  
TIMER1/TIMER3 MODE SELECTION  
16.3 Compare Mode  
Timer1 and/or Timer3 must be running in Timer mode,  
or Synchronized Counter mode, if the CCP module is  
using the compare feature. In Asynchronous Counter  
mode, the compare operation may not work.  
In Compare mode, the 16-bit CCPR1 register value is  
constantly compared against either the TMR1 register  
pair value, or the TMR3 register pair value. When a  
match occurs, the CCP1 pin is:  
• driven High  
• driven Low  
• toggle output (High to Low or Low to High)  
• remains unchanged  
The action on the pin is based on the value of control  
bits, CCP1M3:CCP1M0. At the same time, interrupt  
flag bit CCP1IF (CCP2IF) is set.  
16.3.3  
SOFTWARE INTERRUPT MODE  
When generate software interrupt is chosen, the CCP1  
pin is not affected. Only a CCP interrupt is generated (if  
enabled).  
16.3.4  
SPECIAL EVENT TRIGGER  
In this mode, an internal hardware trigger is generated,  
which may be used to initiate an action.  
The special event trigger output of either CCP1 or  
CCP2, resets the TMR1 or TMR3 register pair, depend-  
ing on which timer resource is currently selected. This  
allows the CCPR1 register to effectively be a 16-bit  
programmable period register for Timer1 or Timer3.  
16.3.1  
CCP PIN CONFIGURATION  
The user must configure the CCPx pin as an output by  
clearing the appropriate TRIS bit.  
Note: Clearing the CCP1CON register will force  
the RC2/CCP1 compare output latch to the  
default low level. This is not the PORTC  
I/O data latch.  
The CCP2 Special Event Trigger will also start an A/D  
conversion if the A/D module is enabled.  
Note: The special event trigger from the CCP2  
module will not set the Timer1 or Timer3  
interrupt flag bits.  
FIGURE 16-3:  
COMPARE MODE OPERATION BLOCK DIAGRAM  
For CCP1 and CCP2 only, the Special Event Trigger will:  
Reset Timer1 or Timer3, but not set Timer1 or Timer3 interrupt flag bit,  
and set bit, GO/DONE (ADCON0<2>)  
which starts an A/D conversion (CCP2 only)  
Special Event Trigger  
Set Flag bit CCP1IF  
CCPR1H CCPR1L  
Comparator  
Q
S
R
Output  
Logic  
Match  
RC2/CCP1 pin  
TRISC<2>  
Output Enable  
1
0
CCP1CON<3:0>  
Mode Select  
T3CCP2  
TMR1H TMR1L  
TMR3H TMR3L  
DS39609A-page 152  
Advance Information  
2003 Microchip Technology Inc.  
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