PIC18FXX20
15.2 Timer4 Interrupt
15.3 Output of TMR4
The Timer4 module has an 8-bit period register, PR4,
which is both readable and writable. Timer4 increments
from 00h until it matches PR4 and then resets to 00h on
the next increment cycle. The PR4 register is initialized
to FFh upon RESET.
The output of TMR4 (before the postscaler) is used
only as a PWM time-base for the CCP modules. It is not
used as a baud rate clock for the MSSP, as is the
Timer2 output.
FIGURE 15-1:
TIMER4 BLOCK DIAGRAM
Sets Flag
TMR4
bit TMR4IF
(1)
Output
Prescaler
1:1, 1:4, 1:16
RESET
EQ
TMR4
FOSC/4
Postscaler
1:1 to 1:16
2
Comparator
PR4
T4CKPS1:T4CKPS0
4
T4OUTPS3:T4OUTPS0
TABLE 15-1: REGISTERS ASSOCIATED WITH TIMER4 AS A TIMER/COUNTER
Value on
all other
RESETS
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TX2IP
TX2IF
TX2IE
RBIE
TMR0IF
INT0IF
RBIF
0000 0000 0000 0000
IPR3
PIR3
PIE3
—
—
—
—
—
—
RC2IP
RC2IF
RC2IE
TMR4IP
TMR4IF
TMR4IE
CCP5IP CCP4IP CCP3IP --11 1111 --00 0000
CCP5IF CCP4IF CCP3IF --00 0000 --00 0000
CCP5IE CCP4IE CCP3IE --00 0000 --00 0000
0000 0000 0000 0000
TMR4
T4CON
PR4
Timer4 Module Register
—
T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 TMR4ON T4CKPS1 T4CKPS0 -000 0000 -000 0000
Timer4 Period Register 1111 1111 1111 1111
Legend: x= unknown, u= unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the Timer4 module.
DS39609A-page 148
Advance Information
2003 Microchip Technology Inc.