PIC18FXX20
When TMR1CS = 0, Timer1 increments every instruc-
tion cycle. When TMR1CS = 1, Timer1 increments on
every rising edge of the external clock input, or the
Timer1 oscillator, if enabled.
12.1 Timer1 Operation
Timer1 can operate in one of these modes:
• As a timer
• As a synchronous counter
• As an asynchronous counter
The Operating mode is determined by the clock select
bit, TMR1CS (T1CON<1>).
When the Timer1 oscillator is enabled (T1OSCEN is
set), the RC1/T1OSI and RC0/T1OSO/T13CKI pins
become inputs. That is, the TRISC<1:0> value is
ignored, and the pins are read as ‘0’.
Timer1 also has an internal “RESET input”. This
RESET can be generated by the CCP module
(Section 16.0).
FIGURE 12-1:
TIMER1 BLOCK DIAGRAM
CCP Special Event Trigger
TMR1IF
Overflow
Interrupt
Flag Bit
Synchronized
Clock Input
TMR1
CLR
0
TMR1L
TMR1H
1
TMR1ON
On/Off
1
T1SYNC
T1OSC
T13CKI/T1OSO
T1OSI
Synchronize
det
T1OSCEN
Enable
Prescaler
1, 2, 4, 8
FOSC/4
Internal
Clock
(1)
Oscillator
0
2
SLEEP Input
T1CKPS1:T1CKPS0
TMR1CS
Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
FIGURE 12-2:
TIMER1 BLOCK DIAGRAM: 16-BIT READ/WRITE MODE
Data Bus<7:0>
8
TMR1H
8
8
Write TMR1L
Read TMR1L
CCP Special Event Trigger
0
TMR1IF
Overflow
Interrupt
Synchronized
Clock Input
TMR1
8
CLR
Timer 1
TMR1L
Flag bit
High Byte
1
TMR1ON
T1SYNC
On/Off
1
T1OSC
T13CKI/T1OSO
Synchronize
det
Prescaler
1, 2, 4, 8
T1OSCEN
Enable
FOSC/4
Internal
0
(1)
T1OSI
Oscillator
Clock
2
SLEEP Input
TMR1CS
T1CKPS1:T1CKPS0
Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
DS39609A-page 136
Advance Information
2003 Microchip Technology Inc.
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