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PIC18LF6720-I/PT 参数 Datasheet PDF下载

PIC18LF6720-I/PT图片预览
型号: PIC18LF6720-I/PT
PDF下载: 下载PDF文件 查看货源
内容描述: 八十〇分之六十四引脚高性能1 Mbit的增强型闪存微控制器与A / D [64/80-Pin High Performance 1 Mbit Enhanced FLASH Microcontrollers with A/D]
分类和应用: 闪存微控制器
文件页数/大小: 366 页 / 6797 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC18FXX20  
FIGURE 10-20:  
PORTJ BLOCK DIAGRAM  
IN I/O MODE  
10.9 PORTJ, TRISJ and LATJ  
Registers  
Note: PORTJ is available only on PIC18F8X20  
RD LATJ  
devices.  
Data  
Bus  
PORTJ is an 8-bit wide, bi-directional port. The corre-  
sponding Data Direction register is TRISJ. Setting a  
TRISJ bit (= 1) will make the corresponding PORTJ pin  
an input (i.e., put the corresponding output driver in a  
High-Impedance mode). Clearing a TRISJ bit (= 0) will  
make the corresponding PORTJ pin an output (i.e., put  
the contents of the output latch on the selected pin).  
D
Q
I/O pin(1)  
WR LATJ  
or  
CK  
Data Latch  
PORTJ  
D
Q
Schmitt  
Trigger  
Input  
The Data Latch register (LATJ) is also memory  
mapped. Read-modify-write operations on the LATJ  
register, read and write the latched output value for  
PORTJ.  
PORTJ is multiplexed with the system bus as the exter-  
nal memory interface; I/O port functions are only avail-  
able when the system bus is disabled. When operating  
as the external memory interface, PORTJ provides the  
control signal to external memory devices. The RJ5 pin  
is not multiplexed with any system bus functions.  
When enabling peripheral functions, care should be  
taken in defining TRIS bits for each PORTJ pin. Some  
peripherals override the TRIS bit to make a pin an out-  
put, while other peripherals override the TRIS bit to  
make a pin an input. The user should refer to the corre-  
sponding peripheral section for the correct TRIS bit  
settings.  
WR TRISJ  
CK  
TRIS Latch  
Buffer  
RD TRISJ  
Q
D
EN  
RD PORTJ  
Note 1: I/O pins have diode protection to VDD and VSS.  
Note: On a Power-on Reset, these pins are  
configured as digital inputs.  
The pin override value is not loaded into the TRIS reg-  
ister. This allows read-modify-write of the TRIS register,  
without concern due to peripheral overrides.  
EXAMPLE 10-9:  
INITIALIZING PORTJ  
; Initialize PORTG by  
; clearing output  
; data latches  
CLRF  
PORTJ  
CLRF  
LATJ  
; Alternate method  
; to clear output  
; data latches  
MOVLW 0xCF  
; Value used to  
; initialize data  
; direction  
MOVWF TRISJ  
; Set RJ3:RJ0 as inputs  
; RJ5:RJ4 as output  
; RJ7:RJ6 as inputs  
2003 Microchip Technology Inc.  
Advance Information  
DS39609A-page 125  
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