PIC18FXX20
FIGURE 1-2:
PIC18F8X20 BLOCK DIAGRAM
Data Bus<8>
PORTA
RA0/AN0
RA1/AN1
RA2/AN2/V
REF
-
RA3/AN3/V
REF
+
RA4/T0CKI
RA5/AN4/SS/LVDIN
RA6
PORTB
RB0/INT0
RB1/INT1
RB2/INT2
RB3/INT3/CCP2
RB4/KBI0
RB5/KBI1/PGM
RB6/KBI2/PGC
RB7/KBI3/PGD
RC0/T1OSO/T13CKI
RC1/T1OSI/CCP2
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX1/CK1
RC7/RX1/DT1
21
21
Table Pointer<21>
8
inc/dec logic
8
Data Latch
Data RAM
Address Latch
System Bus Interface
21
PCLATU PCLATH
12
Address<12>
4
BSR
PCU PCH PCL
Program Counter
Address Latch
Program Memory
Data Latch
TABLELATCH
12
FSR0
FSR1
FSR2
inc/dec
logic
4
Bank0, F
31 Level Stack
12
PORTC
Decode
16
8
ROMLATCH
AD15:AD0, A19:A16
(1)
IR
PORTD
8
PRODH PRODL
PORTE
RD7/PSP7:RD0/PSP0
Instruction
Decode &
Control
Power-up
Timer
Timing
Generation
Oscillator
Start-up Timer
Power-on
Reset
Precision
Bandgap
Reference
Watchdog
Timer
Brown-out
Reset
8 x 8 Multiply
3
BITOP
8
WREG
8
8
ALU<8>
8
8
8
OSC2/CLKO
OSC1/CLKI
RE0/RD
RE1/WR
RE2/CS
RE3
RE4
RE5
RE6
RE7/CCP2
RF0/AN5
RF1/AN6/C2OUT
RF2/AN7/C1OUT
RF3/AN8
RF4/AN9
RF5/AN10/CV
REF
RF6/AN11
RF7/SS
PORTF
PORTG
MCLR
V
DD
, V
SS
RG0/CCP3
RG1/TX2/CK2
RG2/RX2/DT2
RG3/CCP4
RG4/CCP5
RH3:RH0
RH7/AN15:RH4/AN12
PORTH
Synchronous
Serial Port
USART1
USART2
Data
EEPROM
PORTJ
RJ0/ALE
RJ1/OE
RJ2/WRL
RJ3/WRH
RJ4/BA0
RJ5/CE
RJ6/LB
RJ7/UB
10-bit
A/D
BOR
LVD
Timer0
Timer1
Timer2
Timer3
Timer4
Comparator
Note 1:
CCP1
CCP2
CCP3
CCP4
CCP5
External memory interface pins are physically multiplexed with PORTD (AD7:AD0), PORTE (AD15:AD8) and PORTH (A19:A16).
DS39609A-page 10
Advance Information
2003 Microchip Technology Inc.
MICROCHIP [ MICROCHIP TECHNOLOGY ]
