PIC18CXX2
FIGURE 1-2:
PIC18C4X2 BLOCK DIAGRAM
Data Bus<8>
PORTA
21
21
21
Address Latch
Program Memory
(up to 2M Bytes)
Data Latch
31 Level Stack
20
PCLATU PCLATH
Table Pointer <2>
Data Latch
8
8
8
Data RAM
(up to 4K
address reach)
Address Latch
12
Address<12>
4
BSR
(2)
inc/dec logic
RA0/AN0
RA1/AN1
RA2/AN2/V
REF
-
RA3/AN3/V
REF
+
RA4/T0CKI
RA5/AN4/SS/LVDIN
RA6
PCU PCH PCL
Program Counter
12
FSR0
FSR1
FSR2
inc/dec
logic
4
Bank0, F
PORTB
RB0/INT0
RB1/INT1
RB2/INT2
RB3/CCP2
(1)
RB7:RB4
12
16
TABLELATCH
Decode
8
ROMLATCH
PORTC
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
(1)
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK
RC7/RX/DT
Instruction
Register
Instruction
Decode &
Control
OSC2/CLKO
OSC1/CLKI
Timing
Generation
3
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
4X PLL
Watchdog
Timer
Brown-out
Reset
8
PRODH PRODL
8 x 8 Multiply
8
BIT OP
8
WREG
8
8
ALU<8>
8
PORTE
8
PORTD
T1OSI
T1OSO
RD7/PSP7:RD0/PSP0
Precision
Voltage
Reference
RE0/AN5/RD
MCLR
V
DD
, V
SS
RE1/AN6/WR
RE2/AN7/CS
Timer0
Timer1
Timer2
Timer3
A/D Converter
CCP1
CCP2
Master
Synchronous
Serial Port
Addressable
USART
Parallel Slave Port
Note 1:
Optional multiplexing of CCP2 input/output with RB3 is enabled by selection of configuration bit.
2:
The high order bits of the Direct Address for the RAM are from the BSR register (except for the MOVFF
instruction).
3:
Many of the general purpose I/O pins are multiplexed with one or more peripheral module functions.
The multiplexing combinations are device dependent.
©
7/99 Microchip Technology Inc.
Preliminary
DS39026B-page 7
MICROCHIP [ MICROCHIP TECHNOLOGY ]
