PIC18F6525/6621/8525/8621
Pin Diagrams (Cont.’d)
80-Pin TQFP
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
64 63 62 61
RH2/A18
RH3/A19
RJ2/WRL
1
2
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
RJ3/WRH
RE1/AD9/WR/P2C
RE0/AD8/RD/P2D
RG0/ECCP3/P3A
RG1/TX2/CK2
RG2/RX2/DT2
RG3/CCP4/P3D
MCLR/VPP/RG5(3)
RG4/CCP5/P1D
VSS
RB0/INT0/FLT0
RB1/INT1
3
4
RB2/INT2
RB3/INT3/ECCP2(1)/P2A(1)
5
6
RB4/KBI0
7
RB5/KBI1/PGM
RB6/KBI2/PGC
VSS
8
9
PIC18F8525
PIC18F8621
10
11
12
13
14
15
16
17
18
19
20
OSC2/CLKO/RA6
OSC1/CLKI
VDD
VDD
RF7/SS
RB7/KBI3/PGD
RC5/SDO
RF6/AN11
RF5/AN10/CVREF
RF4/AN9
RC4/SDI/SDA
RC3/SCK/SCL
RC2/ECCP1/P1A
RJ7/UB
RF3/AN8
RF2/AN7/C1OUT
RH7/AN15/P1B(2)
RH6/AN14/P1C(2)
RJ6/LB
40
39
21 22 23 24 25 26 27 28 29 30 31 32 33 34
35 36 37 38
Note 1: ECCP2/P2A are multiplexed with RC1 when CCP2MX is set; with RE7 when CCP2MX is cleared and the device
is configured in Microcontroller mode; or with RB3 when CCP2MX is cleared in all other program memory modes.
2: P1B/P1C/P3B/P3C are multiplexed with RE6:RE3 when ECCPMX is set and with RH7:RH4 when ECCPMX is
not set.
3: RG5 is multiplexed with MCLR and is only available when the MCLR Resets are disabled.
2005 Microchip Technology Inc.
DS39612B-page 3
MICROCHIP [ MICROCHIP ]
