PIC18F6525/6621/8525/8621
14.2 Timer1 Oscillator
14.4 Resetting Timer3 Using an ECCP
Special Trigger Output
The Timer1 oscillator may be used as the clock source
for Timer3. The Timer1 oscillator is enabled by setting
the T1OSCEN (T1CON<3>) bit. The oscillator is a low-
power oscillator rated up to 200 kHz. See Section 12.0
“Timer1 Module” for further details.
If either the ECCP1 or ECCP2 module is configured in
Compare mode to generate a special event trigger
(CCP1M3:CCP1M0 = 1011), this signal will reset
Timer3.
Note:
The special event triggers from the ECCP
module will not set interrupt flag bit,
TMR3IF (PIR1<0>).
14.3 Timer3 Interrupt
The TMR3 register pair (TMR3H:TMR3L) increments
from 0000h to FFFFh and rolls over to 0000h. The
TMR3 interrupt, if enabled, is generated on overflow
which is latched in interrupt flag bit, TMR3IF
(PIR2<1>). This interrupt can be enabled/disabled by
setting/clearing TMR3 interrupt enable bit, TMR3IE
(PIE2<1>).
Timer3 must be configured for either Timer or Synchro-
nized Counter mode to take advantage of this feature.
If Timer3 is running in Asynchronous Counter mode,
this Reset operation may not work. In the event that a
write to Timer3 coincides with a special event trigger
from ECCP1, the write will take precedence. In this
mode of operation, the CCPR1H:CCPR1L register pair
effectively becomes the period register for Timer3.
TABLE 14-1: REGISTERS ASSOCIATED WITH TIMER3 AS A TIMER/COUNTER
Value on
all other
Resets
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
GIE/
GIEH
PEIE/
GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
0000 000x 0000 000u
PIR2
—
—
—
CMIF
CMIE
CMIP
—
—
—
EEIF
EEIE
EEIP
BCLIF
BCLIE
BCLIP
LVDIF
LVDIE
LVDIP
TMR3IF
TMR3IE
TMR3IP
CCP2IF -0-0 0000 -0-0 0000
CCP2IE -0-0 0000 -0-0 0000
CCP2IP -1-1 1111 -1-1 1111
xxxx xxxx uuuu uuuu
PIE2
IPR2
TMR3L
TMR3H
T1CON
T3CON
Legend:
Timer3 Register Low Byte
Timer3 Register High Byte
xxxx xxxx uuuu uuuu
RD16
RD16
—
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0-00 0000 u-uu uuuu
T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 0000 0000 uuuu uuuu
x= unknown, u= unchanged, — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer3 module.
2005 Microchip Technology Inc.
DS39612B-page 145
MICROCHIP [ MICROCHIP ]
