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PIC18F8680-I/PT 参数 Datasheet PDF下载

PIC18F8680-I/PT图片预览
型号: PIC18F8680-I/PT
PDF下载: 下载PDF文件 查看货源
内容描述: 64 /68/ 80引脚高性能, 64 KB的增强型闪存微控制器与ECAN模块 [64/68/80-Pin High-Performance, 64-Kbyte Enhanced Flash Microcontrollers with ECAN Module]
分类和应用: 闪存微控制器
文件页数/大小: 496 页 / 8365 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC18F6585/8585/6680/8680  
15.2.3  
SOFTWARE INTERRUPT  
15.2.5  
CAN MESSAGE TIME-STAMP  
When the Capture mode is changed, a false capture  
interrupt may be generated. The user should keep bit  
CCPxIE (PIE registers) clear to avoid false interrupts  
and should clear the flag bit, CCPxIF, following any  
such change in operating mode.  
The CAN capture event occurs when a message is  
received in any of the receive buffers. When config-  
ured, the CAN module provides the trigger to the CCP1  
module to cause a capture event. This feature is  
provided to time-stamp the received CAN messages.  
This feature is enabled by setting the CANCAP bit of  
the CAN I/O Control register (CIOCON<4>). The  
message receive signal from the CAN module then  
takes the place of the events on RC2/CCP1.  
15.2.4  
CCP PRESCALER  
There are four prescaler settings specified by bits  
CCPxM3:CCPxM0. Whenever the CCPx module is  
turned off, or the CCPx module is not in Capture mode,  
the prescaler counter is cleared. This means that any  
Reset will clear the prescaler counter.  
EXAMPLE 15-1:  
CHANGING BETWEEN  
CAPTURE PRESCALERS  
Switching from one capture prescaler to another may  
generate an interrupt. The prescaler counter will not be  
cleared; therefore, the first capture may be from a  
non-zero prescaler. Example 15-1 shows the  
recommended method for switching between capture  
prescalers. This example also clears the prescaler  
counter and will not generate the “false” interrupt.  
CLRF  
MOVLW  
CCP1CON  
NEW_CAPT_PS  
; Turn CCP module off  
; Load WREG with the  
; new prescaler mode  
; value and CCP ON  
; Load CCP1CON with  
; this value  
MOVWF  
CCP1CON  
FIGURE 15-1:  
CAPTURE MODE OPERATION BLOCK DIAGRAM  
TMR3H  
TMR3L  
CCPR1L  
TMR1L  
Set Flag bit CCP1IF  
T3CCP2  
T3CCP2  
TMR3  
Enable  
Prescaler  
÷ 1, 4, 16  
CCP1 pin  
CCPR1H  
TMR1  
and  
Edge Detect  
Enable  
TMR1H  
CCP1CON<3:0>  
Q’s  
Set Flag bit CCP2IF  
T3CCP1  
TMR3H  
TMR3L  
CCPR2L  
TMR1L  
T3CCP2  
TMR3  
Enable  
Prescaler  
÷ 1, 4, 16  
CCP2 pin  
CCPR2H  
TMR1  
and  
Edge Detect  
Enable  
T3CCP2  
T3CCP1  
TMR1H  
CCP2CON<3:0>  
Q’s  
DS30491C-page 170  
2004 Microchip Technology Inc.