PIC18F2331/2431/4331/4431
“core” are described in this section, while those related
to the operation of the peripheral features are
described in the section of that peripheral feature.
6.5.4
SPECIAL FUNCTION REGISTERS
The Special Function Registers (SFRs) are registers
used by the CPU and peripheral modules for controlling
the desired operation of the device. These registers are
implemented as static RAM. A list of these registers is
given in Table 6-1 and Table 6-2.
The SFRs are typically distributed among the
peripherals whose functions they control.
The unused SFR locations will be unimplemented and
read as ‘0’s.
The SFRs can be classified into two sets: those asso-
ciated with the “core” function and those related to the
peripheral functions. Those registers related to the
TABLE 6-1:
SPECIAL FUNCTION REGISTER MAP FOR PIC18F2331/2431/4331/4431 DEVICES
Address
FFFh
Name
TOSU
TOSH
TOSL
Address
Name
Address
Name
Address
F9Fh
Name
IPR1
PIR1
PIE1
Address
F7Fh
F7Eh
F7Dh
F7Ch
F7Bh
F7Ah
F79h
F78h
F77h
F76h
F75h
F74h
F73h
F72h
F71h
F70h
F6Fh
F6Eh
F6Dh
F6Ch
F6Bh
F6Ah
F69h
F68h
F67h
F66h
F65h
F64h
F63h
F62h
F61h
F60h
Name
PTCON0
PTCON1
PTMRL
PTMRH
PTPERL
PTPERH
PDC0L
(1)
FDFh
INDF2
FBFh CCPR1H
FBEh CCPR1L
FBDh CCP1CON
FBCh CCPR2H
FBBh CCPR2L
FBAh CCP2CON
FB9h ANSEL1
FB8h ANSEL0
(1)
(1)
FFEh
FDEh POSTINC2
F9Eh
FFDh
FDDh POSTDEC2
F9Dh
(1)
(2)
FFCh
FFBh
FFAh
FF9h
FF8h
FF7h
FF6h
FF5h
FF4h
FF3h
FF2h
FF1h
FF0h
FEFh
STKPTR
PCLATU
PCLATH
PCL
FDCh PREINC2
F9Ch
—
(1)
FDBh
FDAh
FD9h
FD8h
FD7h
FD6h
FD5h
FD4h
FD3h
FD2h
FD1h
FD0h
FCFh
FCEh
FCDh
FCCh
FCBh
FCAh
FC9h
FC8h
FC7h
FC6h
FC5h
FC4h
FC3h
FC2h
FC1h
FC0h
PLUSW2
F9Bh OSCTUNE
F9Ah ADCON3
FSR2H
FSR2L
F99h
F98h
F97h
ADCHS
(2)
TBLPTRU
TBLPTRH
TBLPTRL
TABLAT
PRODH
PRODL
STATUS
TMR0H
TMR0L
T0CON
—
PDC0H
PDC1L
(2)
FB7h
T5CON
—
(3)
FB6h QEICON
F96h TRISE
F95h TRISD
PDC1H
PDC2L
(2)
(3)
FB5h
FB4h
FB3h
FB2h
FB1h
—
—
—
—
—
(2)
(2)
(2)
(2)
(2)
—
F94h
F93h
F92h
F91h
F90h
F8Fh
F8Eh
F8Dh
F8Ch
F8Bh
F8Ah
F89h
F88h
F87h
F86h
F85h
F84h
TRISC
PDC2H
(3)
OSCCON
LVDCON
WDTCON
RCON
TRISB
TRISA
PR5H
PR5L
PDC3L
(3)
INTCON
INTCON2
INTCON3
PDC3H
SEVTCMPL
SEVTCMPH
PWMCON0
PWMCON1
DTCON
FB0h SPBRGH
(1)
(2)
INDF0
TMR1H
TMR1L
FAFh
FAEh
FADh
FACh
FABh
SPBRG
RCREG
TXREG
TXSTA
RCSTA
—
(1)
(1)
(2)
FEEh POSTINC0
—
(3)
FEDh POSTDEC0
T1CON
TMR2
LATE
(1)
(3)
FECh PREINC0
LATD
FLTCONFIG
OVDCOND
OVDCONS
CAP1BUFH
CAP1BUFL
CAP2BUFH
CAP2BUFL
CAP3BUFH
CAP3BUFL
CAP1CON
CAP2CON
CAP3CON
DFLTCON
(1)
FEBh PLUSW0
PR2
LATC
LATB
FEAh
FE9h
FE8h
FE7h
FSR0H
FSR0L
WREG
T2CON
SSPBUF
SSPADD
SSPSTAT
SSPCON
FAAh BAUDCON
FA9h EEADR
LATA
FA8h EEDATA
FA7h EECON2
FA6h EECON1
TMR5H
TMR5L
(1)
INDF1
(1)
(1)
(2)
FE6h POSTINC1
—
(2)
(2)
FE5h POSTDEC1
—
FA5h
FA4h
FA3h
FA2h
FA1h
FA0h
IPR3
PIR3
PIE3
IPR2
PIR2
PIE2
—
(1)
FE4h PREINC1
ADRESH
ADRESL
ADCON0
ADCON1
ADCON2
PORTE
(1)
(3)
FE3h PLUSW1
F83h PORTD
FE2h
FE1h
FE0h
FSR1H
FSR1L
BSR
F82h
F81h
F80h
PORTC
PORTB
PORTA
Note 1: This is not a physical register.
2: Unimplemented registers are read as ‘0’.
3: This register is not available on 28-pin devices.
2010 Microchip Technology Inc.
DS39616D-page 69
MICROCHIP [ MICROCHIP ]
