PIC18F2331/2431/4331/4431
FIGURE 1-2:
PIC18F4331/4431 (40/44-PIN) BLOCK DIAGRAM
Data Bus<8>
PORTA
RA0/AN0
RA1/AN1
RA2/AN2/VREF-/CAP1/INDX
RA3/AN3/VREF+/CAP2/QEA
RA4/AN4/CAP3/QEB
RA5/AN5/LVDIN
Table Pointer<21>
inc/dec logic
Data Latch
21
8
8
Data RAM
(768 bytes)
21
21
Address Latch
12
OSC2/CLKO/RA6
OSC1/CLKI/RA7
20
PCLATU PCLATH
Address Latch
Address<12>
Program Memory
PCU PCH PCL
Program Counter
PORTB
4
12
4
RB0/PWM0
Data Latch
BSR
Bank 0, F
FSR0
FSR1
FSR2
RB1/PWM1
RB2/PWM2
RB3/PWM3
31 Level Stack
12
RB4/KBI0/PWM5
RB5/KBI1/PWM4/PGM
RB6/KBI2/PGC
RB7/KBI3/PGD
16
inc/dec
logic
Decode
Table Latch
8
ROM Latch
IR
PORTC
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2/FLTA
RC2/CCP1/FLTB
RC3/T0CKI/T5CKI/INT0(3)
RC4/INT1/SDI/SDA(3)
8
RC5/INT2/SCK/SCL(3)
RC6/TX/CK/SS
Instruction
Decode &
Control
RC7/RX/DT/SDO
PRODH PRODL
8 x 8 Multiply
3
Power-up
Timer
OSC2/CLKO
OSC1/CLKI
T1OSI
8
PORTD
RD0/IT0CKI/T5CKI
RD1/SDO
RD2/SDI/SDA
Timing
Generation
W
8
BITOP
8
Oscillator
Start-up Timer
8
RD3/SCK/SCL
RD4/FLTA(2)
RD5/PWM4(4)
RD6/PWM6
Power-on
Reset
8
T1OSO
4x PLL
ALU<8>
Watchdog
Timer
RD7/PWM7
8
Precision
Band Gap
Reference
Brown-out
Reset
PORTE
RE0/AN6
Power-Managed
Mode Logic
MCLR/VPP
RE1/AN7
RE2/AN8
INTRC
OSC
MCLR/VPP/RE3(1)
VDD, VSS
Timer0
HS 10-Bit
ADC
Timer1
Timer2
Timer5
AVDD, AVSS
Synchronous
Serial Port
CCP1
CCP2
EUSART
Data EE
PCPWM
MFM
Note 1: RE3 is available only when MCLR is disabled.
2: RD4 is the alternate pin for FLTA.
3: RC3, RC4 and RC5 are alternate pins for T0CKI/T5CKI, SDI/SDA, SCK/SCL, respectively.
4: RD5 is the alternate pin for PWM4.
2010 Microchip Technology Inc.
DS39616D-page 15
MICROCHIP [ MICROCHIP ]
