PIC18F2331/2431/4331/4431
FIGURE 10-1:
INTERRUPT LOGIC
Wake-up if in
Power-Managed Mode
TMR0IF
TMR0IE
TMR0IP
RBIF
RBIE
RBIP
INT0IF
INT0IE
Interrupt to CPU
Vector to Location
0008h
INT1IF
INT1IE
INT1IP
INT2IF
INT2IE
INT2IP
TXIF
TXIE
TXIP
GIE/GIEH
ADIF
ADIE
ADIP
IPEN
IPEN
PEIE/GIEL
RCIF
RCIE
RCIP
IPEN
Additional Peripheral Interrupts
High-Priority Interrupt Generation
Low-Priority Interrupt Generation
TXIF
TXIE
TXIP
Interrupt to CPU
Vector to Location
0018h
TMR0IF
TMR0IE
TMR0IP
ADIF
ADIE
ADIP
RBIF
RBIE
RBIP
RCIF
RCIE
RCIP
PEIE/GIEL
INT0IF
INT0IE
INT1IF
INT1IE
INT1IP
Additional Peripheral Interrupts
INT2IF
INT2IE
INT2IP
DS39616D-page 98
2010 Microchip Technology Inc.