PIC18F2331/2431/4331/4431
FIGURE 8-2:
TABLE WRITE OPERATION
Instruction: TBLWT*
Program Memory
Holding Registers
(1)
Table Pointer
Table Latch (8-bit)
TABLAT
TBLPTRU TBLPTRH TBLPTRL
Program Memory
(TBLPTR)
Note 1: The Table Pointer actually points to one of eight holding registers, the address of which is determined
by TBLPTRL<2:0>. The process for physically writing data to the program memory array is discussed
in Section 8.5 “Writing to Flash Program Memory”.
The FREE bit controls program memory erase opera-
tions. When the FREE bit is set, the erase operation is
initiated on the next WR command. When FREE is
clear, only writes are enabled.
8.2
Control Registers
Several control registers are used in conjunction with
the TBLRDand TBLWTinstructions. These include the:
• EECON1 register
• EECON2 register
• TABLAT register
• TBLPTR registers
A write operation is allowed when the WREN bit
(EECON1<2>) is set. On power-up, the WREN bit is
clear. The WRERR bit (EECON1<3>) is set in hard-
ware when the WR bit (EECON1<1>) is set and
cleared when the internal programming timer expires
and the write operation is complete.
8.2.1
EECON1 AND EECON2 REGISTERS
EECON1 is the control register for memory accesses.
Note:
During normal operation, the WRERR
may read as ‘1’. This can indicate that a
write operation was prematurely termi-
nated by a Reset or a write operation was
attempted improperly.
EECON2 is not a physical register. Reading EECON2
will read all ‘0’s. The EECON2 register is used
exclusively in the memory write and erase sequences.
Control bit, EEPGD, determines if the access will be to
program or data EEPROM memory. When clear,
operations will access the data EEPROM memory.
When set, program memory is accessed.
The WR control bit initiates write operations. The bit
cannot be cleared, only set, in software. The bit is
cleared in hardware at the completion of the write
operation.
Control bit, CFGS, determines if the access will be to
the Configuration registers or to program memory/data
EEPROM memory. When set, subsequent operations
access Configuration registers, regardless of EEPGD.
(See Section 23.0 “Special Features of the CPU”.)
When CFGS is clear, the EEPGD bit selects either
program Flash or data EEPROM memory.
Note:
The EEIF interrupt flag bit (PIR2<4>) is
set when the write is complete. It must be
cleared in software.
DS39616D-page 86
2010 Microchip Technology Inc.
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