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PIC18F4431-I/P 参数 Datasheet PDF下载

PIC18F4431-I/P图片预览
型号: PIC18F4431-I/P
PDF下载: 下载PDF文件 查看货源
内容描述: 28 /40/ 44引脚增强型闪存微控制器采用纳瓦技术,高性能PWM和A / D [28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High-Performance PWM and A/D]
分类和应用: 闪存微控制器
文件页数/大小: 392 页 / 3127 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC18F2331/2431/4331/4431  
After a write sequence has been initiated, EECON1,  
EEADR and EEDATA cannot be modified. The WR bit  
will be inhibited from being set unless the WREN bit is  
7.3  
Reading the Data EEPROM  
Memory  
To read a data memory location, the user must write the  
address to the EEADR register, clear the EEPGD con-  
trol bit (EECON1<7>) and then set control bit, RD  
(EECON1<0>). The data is available for the very next  
instruction cycle; therefore, the EEDATA register can  
be read by the next instruction. EEDATA will hold this  
value until another read operation, or until it is written to  
by the user (during a write operation).The basic  
process is shown in Example 7-1.  
set. The WREN bit must be set on a previous instruc-  
tion. Both WR and WREN cannot be set with the same  
instruction.  
At the completion of the write cycle, the WR bit is  
cleared in hardware and the EEPROM Interrupt Flag bit  
(EEIF) is set. The user may either enable this interrupt  
or poll this bit. EEIF must be cleared by software.  
7.5  
Write Verify  
7.4  
Writing to the Data EEPROM  
Memory  
Depending on the application, good programming  
practice may dictate that the value written to the mem-  
ory should be verified against the original value. This  
should be used in applications where excessive writes  
can stress bits near the specification limit.  
To write an EEPROM data location, the address must  
first be written to the EEADR register and the data writ-  
ten to the EEDATA register. The sequence in  
Example 7-2 must be followed to initiate the write cycle.  
7.6  
Protection Against Spurious Write  
The write will not begin if this sequence is not exactly  
followed (write 55h to EECON2, write 0AAh to  
EECON2, then set WR bit) for each byte. It is strongly  
recommended that interrupts be disabled during this  
code segment.  
There are conditions when the device may not want to  
write to the data EEPROM memory. To protect against  
spurious EEPROM writes, various mechanisms have  
been built-in. On power-up, the WREN bit is cleared.  
Also, the Power-up Timer (72 ms duration) prevents  
EEPROM write.  
Additionally, the WREN bit in EECON1 must be set to  
enable writes. This mechanism prevents accidental  
writes to data EEPROM due to unexpected code exe-  
cution (i.e., runaway programs). The WREN bit should  
be kept clear at all times, except when updating the  
EEPROM. The WREN bit is not cleared by hardware.  
The write initiate sequence and the WREN bit together  
help prevent an accidental write during brown-out,  
power glitch, or software malfunction.  
EXAMPLE 7-1:  
DATA EEPROM READ  
MOVLW  
MOVWF  
BCF  
BSF  
MOVF  
DATA_EE_ADDR  
EEADR  
EECON1, EEPGD  
EECON1, RD  
EEDATA, W  
;
; Data Memory Address to read  
; Point to DATA memory  
; EEPROM Read  
; W = EEDATA  
EXAMPLE 7-2:  
DATA EEPROM WRITE  
MOVLW  
MOVWF  
MOVLW  
MOVWF  
BCF  
BCF  
BSF  
BCF  
MOVLW  
MOVWF  
MOVLW  
MOVWF  
BSF  
DATA_EE_ADDR  
EEADR  
DATA_EE_DATA  
EEDATA  
EECON1, EEPGD  
EECON1, CFGS  
EECON1, WREN  
INTCON, GIE  
55h  
EECON2  
0AAh  
EECON2  
EECON1, WR  
EECON1, WR  
;
; Data Memory Address to write  
;
; Data Memory Value to write  
; Point to DATA memory  
; Access EEPROM  
; Enable writes  
; Disable Interrupts  
;
; Write 55h  
;
; Write 0AAh  
; Set WR bit to begin write  
; Wait for write to complete  
Required  
Sequence  
BTFSC  
GOTO  
BSF  
$-2  
INTCON, GIE  
;
; Enable interrupts  
2010 Microchip Technology Inc.  
DS39616D-page 81  
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