PIC18F2331/2431/4331/4431
RETFIE
Return from Interrupt
RETLW
Return Literal to W
Syntax:
[ label ] RETFIE [s]
s [0,1]
Syntax:
[ label ] RETLW
0 k 255
k
Operands:
Operation:
Operands:
Operation:
(TOS) PC,
k W,
1 GIE/GIEH or PEIE/GIEL;
if s = 1:
(TOS) PC,
PCLATU, PCLATH are unchanged
(WS) W,
(STATUSS) STATUS,
(BSRS) BSR,
Status Affected:
Encoding:
None
0000
1100
kkkk
kkkk
PCLATU, PCLATH are unchanged
Description:
W is loaded with the 8-bit literal, ‘k’. The
program counter is loaded from the top
of the stack (the return address). The
high address latch (PCLATH) remains
unchanged.
Status Affected:
Encoding:
GIE/GIEH, PEIE/GIEL.
0000
0000
0001
000s
Description:
Return from interrupt. Stack is popped
and Top-of-Stack (TOS) is loaded into
the PC. Interrupts are enabled by
setting either the high or low-priority
global interrupt enable bit. If ‘s’ = 1, the
contents of the shadow registers, WS,
STATUSS and BSRS, are loaded into
their corresponding registers, W,
STATUS and BSR. If ‘s’ = 0, no update
of these registers occurs.
Words:
Cycles:
1
2
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal ‘k’
Process
Data
POP PC
from stack,
Write to W
No
operation
No
No
No
Words:
Cycles:
1
2
operation
operation
operation
Q Cycle Activity:
Q1
Example:
Q2
Q3
Q4
CALL TABLE ; W contains table
; offset value
Decode
No
operation
No
operation
POP PC
from stack
; W now has
; table value
Set GIEH or
GIEL
:
No
operation
No
operation
No
operation
No
operation
TABLE
ADDWF PCL ; W = offset
RETLW k0
RETLW k1
:
; Begin table
;
Example:
RETFIE
1
After Interrupt
:
PC
W
BSR
STATUS
=
=
=
=
=
TOS
WS
BSRS
STATUSS
1
RETLW kn
; End of table
Before Instruction
W
=
0x07
GIE/GIEH, PEIE/GIEL
After Instruction
W
=
value of kn
DS39616D-page 314
2010 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
