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PIC18F4431-I/P 参数 Datasheet PDF下载

PIC18F4431-I/P图片预览
型号: PIC18F4431-I/P
PDF下载: 下载PDF文件 查看货源
内容描述: 28 /40/ 44引脚增强型闪存微控制器采用纳瓦技术,高性能PWM和A / D [28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High-Performance PWM and A/D]
分类和应用: 闪存微控制器
文件页数/大小: 392 页 / 3127 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC18F2331/2431/4331/4431  
An external clock source may also be connected to the  
OSC1 pin in the HS mode, as shown in Figure 3-2.  
TABLE 3-2:  
CAPACITOR SELECTION FOR  
CRYSTAL OSCILLATOR  
Typical Capacitor Values  
FIGURE 3-2:  
EXTERNAL CLOCK INPUT  
OPERATION (HS OSC  
CONFIGURATION)  
Crystal  
Freq  
Tested:  
Osc Type  
C1  
C2  
LP  
XT  
HS  
32 kHz  
200 kHz  
1 MHz  
4 MHz  
4 MHz  
8 MHz  
20 MHz  
33 pF  
15 pF  
33 pF  
27 pF  
27 pF  
22 pF  
15 pF  
33 pF  
15 pF  
33 pF  
27 pF  
27 pF  
22 pF  
15 pF  
OSC1  
Clock from  
Ext. System  
PIC18FXXXX  
(HS Mode)  
OSC2  
Open  
3.3  
PLL Frequency Multiplier  
Capacitor values are for design guidance only.  
A Phase Locked Loop (PLL) circuit is provided as an  
option for users who wish to use a lower frequency  
oscillator circuit or to clock the device up to its highest  
rated frequency from a crystal oscillator. This may be  
useful for those concerned with EMI from high-  
frequency crystals or users requiring higher clock  
speeds from an internal oscillator.  
These capacitors were tested with the crystals listed  
below for basic start-up and operation. These values  
are not optimized.  
Different capacitor values may be required to produce  
acceptable oscillator operation. The user should test  
the performance of the oscillator over the expected  
VDD and temperature range for the application.  
3.3.1  
HSPLL OSCILLATOR MODE  
See the notes following this table for additional  
information.  
The HSPLL mode uses the HS Oscillator mode for  
frequencies up to 10 MHz. A PLL circuit then multiplies  
the oscillator output frequency by four to produce an  
internal clock frequency up to 40 MHz. The PLLEN bit  
is not available in this oscillator mode.  
Crystals Used:  
32 kHz  
200 kHz  
1 MHz  
4 MHz  
8 MHz  
20 MHz  
The PLL is only available to the crystal oscillator when  
the FOSC<3:0> Configuration bits are programmed for  
HSPLL mode (‘0110’).  
Note 1: Higher capacitance increases the  
stability of oscillator, but also increases  
the start-up time.  
FIGURE 3-3:  
PLL BLOCK DIAGRAM  
HS Osc Enable  
PLL Enable  
2: When operating below 3V VDD, or when  
using certain ceramic resonators at any  
voltage, it may be necessary to use the  
HS mode or switch to a crystal oscillator.  
(from Configuration Register 1H)  
OSC2  
OSC1  
Phase  
Comparator  
3: Since each resonator/crystal has its own  
characteristics, the user should consult  
the resonator/crystal manufacturer for  
HS Mode  
Crystal  
Osc  
FIN  
FOUT  
appropriate  
components.  
values  
of  
external  
Loop  
Filter  
4: Rs may be required to avoid overdriving  
crystals with low drive level specification.  
4  
VCO  
5: Always verify oscillator performance over  
the VDD and temperature range that is  
expected for the application.  
SYSCLK  
DS39616D-page 30  
2010 Microchip Technology Inc.  
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