PIC18F2331/2431/4331/4431
Each of the five blocks has three code protection bits
associated with them. They are:
23.5 Program Verification and
Code Protection
• Code-Protect bit (CPn)
The overall structure of the code protection on the
PIC18 Flash devices differs significantly from other
PIC® devices.
• Write-Protect bit (WRTn)
• External Block Table Read bit (EBTRn)
Figure 23-5 shows the program memory organization
for 8 and 16-Kbyte devices, and the specific code
protection bit associated with each block. The actual
locations of the bits are summarized in Table 23-3.
The user program memory is divided into five blocks.
One of these is a Boot Block of 512 bytes. The
remainder of the memory is divided into four blocks on
binary boundaries.
FIGURE 23-5:
CODE-PROTECTED PROGRAM MEMORY FOR PIC18F2331/2431/4331/4431
MEMORY SIZE/DEVICE
Block Code Protection
Controlled By:
8 Kbytes
(PIC18F2331/4331)
Address
Range
16 Kbytes
(PIC18F2431/4431)
Address
Range
0000h
0FFFh
0000h
01FFh
Boot Block
Boot Block
Block 0
CPB, WRTB, EBTRB
CP0, WRT0, EBTR0
0200h
0200h
Block 0
Block 1
0FFFh
1000h
0FFFh
1000h
Block 1
Block 2
Block 3
CP1, WRT1, EBTR1
CP2, WRT2, EBTR2
CP3, WRT3, EBTR3
1FFFh
1FFFh
2000h
2FFFh
3000h
Unimplemented
Read ‘0’s
3FFFh
3FFFh
TABLE 23-3: SUMMARY OF CODE PROTECTION REGISTERS
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
300008h
CONFIG5L
CONFIG5H
CONFIG6L
—
CPD
—
—
CPB
—
—
—
—
—
—
—
—
—
CP3(1)
CP2(1)
CP1
—
CP0
—
300009h
30000Ah
30000Bh
30000Ch
30000Dh
—
—
—
WRT3(1) WRT2(1)
WRT1
WRT0
—
CONFIG6H WRTD
WRTB
—
WRTC
—
—
—
—
CONFIG7L
CONFIG7H
—
—
EBTR3(1) EBTR2(1) EBTR1
EBTR0
—
EBTRB
—
—
—
—
Legend: Shaded cells are unimplemented.
Note 1: Unimplemented in PIC18F2331/4331 devices; maintain this bit set.
2010 Microchip Technology Inc.
DS39616D-page 279
MICROCHIP [ MICROCHIP ]
