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PIC18F4431-I/P 参数 Datasheet PDF下载

PIC18F4431-I/P图片预览
型号: PIC18F4431-I/P
PDF下载: 下载PDF文件 查看货源
内容描述: 28 /40/ 44引脚增强型闪存微控制器采用纳瓦技术,高性能PWM和A / D [28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High-Performance PWM and A/D]
分类和应用: 闪存微控制器
文件页数/大小: 392 页 / 3127 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC18F2331/2431/4331/4431  
23.2 Watchdog Timer (WDT)  
Note 1: The CLRWDT and SLEEP instructions  
clear the WDT and postscaler counts  
when executed.  
For PIC18F2331/2431/4331/4431 devices, the WDT is  
driven by the INTRC source. When the WDT is  
enabled, the clock source is also enabled. The nominal  
WDT period is 4 ms and has the same stability as the  
INTRC oscillator.  
2: Changing the setting of the IRCF bits  
(OSCCON<6:4>) clears the WDT and  
postscaler counts.  
The 4 ms period of the WDT is multiplied by a 16-bit  
postscaler. Any output of the WDT postscaler is  
3: When a CLRWDTinstruction is executed,  
the postscaler count will be cleared.  
selected by  
a multiplexer, controlled by bits in  
4: If WINEN = 0, then CLRWDTmust be exe-  
cuted only when WDTW = 1; otherwise, a  
device Reset will result.  
Configuration Register 2H (see Register 23-3).  
Available periods range from 4 ms to 131.072 seconds  
(2.18 minutes). The WDT and postscaler are cleared  
when any of the following events occur: execute a  
SLEEP or CLRWDT instruction, the IRCF bits  
(OSCCON<6:4>) are changed or a clock failure has  
occurred (see Section 23.4.1 “FSCM and the  
Watchdog Timer”).  
23.2.1  
CONTROL REGISTER  
Register 23-15 shows the WDTCON register. This is a  
readable and writable register. The SWDTEN bit allows  
software to enable or disable the WDT, but only if the  
Configuration bit has disabled the WDT. The WDTW bit  
is a read-only bit that indicates when the WDT count is  
in the fourth quadrant (i.e., when the 8-bit WDT value is  
b11000000’ or greater).  
Adjustments to the internal oscillator clock period using  
the OSCTUNE register also affect the period of the  
WDT by the same factor. For example, if the INTRC  
period is increased by 3%, then the WDT period is  
increased by 3%.  
FIGURE 23-1:  
WDT BLOCK DIAGRAM  
Enable WDT  
SWDTEN  
INTRC Control  
WDT Counter  
125  
WDTEN  
Wake-up  
from Sleep  
INTRC Source  
Change on IRCF bits  
CLRWDT  
WDT  
Reset  
Reset  
Programmable Postscaler  
1:1 to 1:32,768  
All Device Resets  
WDT  
4
WDTPS<3:0>  
Sleep  
DS39616D-page 274  
2010 Microchip Technology Inc.  
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