欢迎访问ic37.com |
会员登录 免费注册
发布采购

PIC18F4431-I/PT 参数 Datasheet PDF下载

PIC18F4431-I/PT图片预览
型号: PIC18F4431-I/PT
PDF下载: 下载PDF文件 查看货源
内容描述: 28 /40/ 44引脚增强型闪存微控制器采用纳瓦技术,高性能PWM和A / D [28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High-Performance PWM and A/D]
分类和应用: 闪存微控制器
文件页数/大小: 392 页 / 3127 K
品牌: MICROCHIP [ MICROCHIP ]
 浏览型号PIC18F4431-I/PT的Datasheet PDF文件第90页浏览型号PIC18F4431-I/PT的Datasheet PDF文件第91页浏览型号PIC18F4431-I/PT的Datasheet PDF文件第92页浏览型号PIC18F4431-I/PT的Datasheet PDF文件第93页浏览型号PIC18F4431-I/PT的Datasheet PDF文件第95页浏览型号PIC18F4431-I/PT的Datasheet PDF文件第96页浏览型号PIC18F4431-I/PT的Datasheet PDF文件第97页浏览型号PIC18F4431-I/PT的Datasheet PDF文件第98页  
PIC18F2331/2431/4331/4431  
EXAMPLE 8-3:  
WRITING TO FLASH PROGRAM MEMORY (CONTINUED)  
PROGRAM_MEMORY  
BCF  
INTCON, GIE  
55h  
EECON2  
0AAh  
EECON2  
; disable interrupts  
; required sequence  
; write 55h  
MOVLW  
MOVWF  
MOVLW  
MOVWF  
BSF  
; write 0AAh  
; start program (CPU stall)  
EECON1, WR  
NOP  
BSF  
INTCON, GIE  
; re-enable interrupts  
; loop until done  
DECFSZ COUNTER_HI  
GOTO  
BCF  
PROGRAM_LOOP  
EECON1, WREN  
; disable write to memory  
reprogrammed if needed. The WRERR bit is set when  
8.5.2  
WRITE VERIFY  
a write operation is interrupted by a MCLR Reset, or a  
WDT Time-out Reset during normal operation. In these  
situations, users can check the WRERR bit and rewrite  
the location.  
Depending on the application, good programming  
practice may dictate that the value written to the  
memory should be verified against the original value.  
This should be used in applications where excessive  
writes can stress bits near the specification limit.  
8.6  
Flash Program Operation During  
Code Protection  
8.5.3  
UNEXPECTED TERMINATION OF  
WRITE OPERATION  
See Section 23.5 “Program Verification and Code  
Protection” for details on code protection of Flash  
program memory.  
If a write is terminated by an unplanned event, such as  
loss of power or an unexpected Reset, the memory  
location just programmed should be verified and  
TABLE 8-2:  
Name  
REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY  
Reset  
Values  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
on Page:  
TBLPTRU  
bit 21(1) Program Memory Table Pointer Upper Byte (TBLPTR<20:16>)  
54  
54  
54  
54  
54  
56  
56  
57  
57  
57  
TBPLTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>)  
TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>)  
TABLAT Program Memory Table Latch  
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE  
RBIE  
TMR0IF  
INT0IF  
RBIF  
EECON2 EEPROM Control Register 2 (not a physical register)  
EECON1 EEPGD  
CFGS  
FREE  
EEIP  
EEIF  
EEIE  
WRERR  
WREN  
LVDIP  
LVDIF  
LVDIE  
WR  
RD  
IPR2  
PIR2  
PIE2  
OSCFIP  
OSCFIF  
OSCFIE  
CCP2IP  
CCP2IF  
CCP2IE  
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access.  
Note 1: Bit 21 of the PC is only available in Test mode and Serial Programming modes.  
DS39616D-page 94  
2010 Microchip Technology Inc.  
 复制成功!